rpc: add public Records as module ports.

This commit is contained in:
Jean-François Nguyen 2019-09-30 00:12:17 +02:00 committed by whitequark
parent 52f36025a9
commit 905920aa76

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@ -3,7 +3,7 @@ import json
import argparse import argparse
import importlib import importlib
from .hdl import Signal, Elaboratable from .hdl import Signal, Record, Elaboratable
from .back import rtlil from .back import rtlil
@ -68,13 +68,12 @@ def _serve_yosys(modules):
try: try:
elaboratable = modules[module_name](*args, **kwargs) elaboratable = modules[module_name](*args, **kwargs)
def has_port(elaboratable, port_name): ports = []
# By convention, any public attribute that is a Signal is considered a port. # By convention, any public attribute that is a Signal or a Record is
return (not port_name.startswith("_") and # considered a port.
isinstance(getattr(elaboratable, port_name), Signal)) for port_name, port in vars(elaboratable).items():
ports = [getattr(elaboratable, port_name) if not port_name.startswith("_") and isinstance(port, (Signal, Record)):
for port_name in dir(elaboratable) ports += port._lhs_signals()
if has_port(elaboratable, port_name)]
rtlil_text = rtlil.convert(elaboratable, name=module_name, ports=ports) rtlil_text = rtlil.convert(elaboratable, name=module_name, ports=ports)
response = {"frontend": "ilang", "source": rtlil_text} response = {"frontend": "ilang", "source": rtlil_text}
except Exception as error: except Exception as error: