back.pysim: don't crash when trying to drive a nonexistent domain clock.

nmigen/back/pysim.py

@@ -451,6 +451,10 @@ class Simulator:
         for domain_obj in self._domains:
             if not domain_obj.local and domain_obj.name == domain:
                 clk = domain_obj.clk
+                break
+        else:
+            raise ValueError("Domain '{}' is not present in simulation"
+                             .format(domain))
         def clk_process():
             yield Passive()
             yield Delay(phase)

nmigen/test/test_sim.py

@@ -413,6 +413,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
                     msg="Domain 'sync' already has a clock driving it"):
                 sim.add_clock(1)
 
+    def test_add_clock_wrong(self):
+        m = Module()
+        with self.assertSimulation(m) as sim:
+            with self.assertRaises(ValueError,
+                    msg="Domain 'sync' is not present in simulation"):
+                sim.add_clock(1)
+
     def test_eq_signal_unused_wrong(self):
         self.setUp_lhs_rhs()
         self.s = Signal()