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back.pysim: don't crash when trying to drive a nonexistent domain clock.

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This commit is contained in:
whitequark 2019-08-23 08:37:59 +00:00
parent 9350620f89
commit 906385c7f8
2 changed files with 11 additions and 0 deletions
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4
nmigen/back/pysim.py
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@ -451,6 +451,10 @@ class Simulator:
for domain_obj in self._domains: for domain_obj in self._domains:
if not domain_obj.local and domain_obj.name == domain: if not domain_obj.local and domain_obj.name == domain:
clk = domain_obj.clk clk = domain_obj.clk
break
else:
raise ValueError("Domain '{}' is not present in simulation"
.format(domain))
def clk_process(): def clk_process():
yield Passive() yield Passive()
yield Delay(phase) yield Delay(phase)

7
nmigen/test/test_sim.py
View file

@ -413,6 +413,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
msg="Domain 'sync' already has a clock driving it"): msg="Domain 'sync' already has a clock driving it"):
sim.add_clock(1) sim.add_clock(1)
def test_add_clock_wrong(self):
m = Module()
with self.assertSimulation(m) as sim:
with self.assertRaises(ValueError,
msg="Domain 'sync' is not present in simulation"):
sim.add_clock(1)
def test_eq_signal_unused_wrong(self): def test_eq_signal_unused_wrong(self):
self.setUp_lhs_rhs() self.setUp_lhs_rhs()
self.s = Signal() self.s = Signal()