Rename nMigen to Amaranth HDL.

examples/basic/alu.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 class ALU(Elaboratable):

examples/basic/alu_hier.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 class Adder(Elaboratable):

examples/basic/arst.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 class ClockDivisor(Elaboratable):

examples/basic/cdc.py

@@ -1,6 +1,6 @@
-from nmigen import *
-from nmigen.lib.cdc import FFSynchronizer
-from nmigen.cli import main
+from amaranth import *
+from amaranth.lib.cdc import FFSynchronizer
+from amaranth.cli import main
 
 
 i, o = Signal(name="i"), Signal(name="o")

examples/basic/ctr.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 class Counter(Elaboratable):

examples/basic/ctr_en.py

@@ -1,6 +1,6 @@
-from nmigen import *
-from nmigen.sim import *
-from nmigen.back import verilog
+from amaranth import *
+from amaranth.sim import *
+from amaranth.back import verilog
 
 
 class Counter(Elaboratable):

examples/basic/fsm.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 class UARTReceiver(Elaboratable):

examples/basic/gpio.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 class GPIO(Elaboratable):

examples/basic/inst.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 class System(Elaboratable):

examples/basic/mem.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 class RegisterFile(Elaboratable):

examples/basic/pmux.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 class ParMux(Elaboratable):

examples/basic/por.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 m = Module()

examples/basic/sel.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.cli import main
+from amaranth import *
+from amaranth.cli import main
 
 
 class FlatGPIO(Elaboratable):

examples/basic/uart.py

@@ -1,4 +1,4 @@
-from nmigen import *
+from amaranth import *
 
 
 class UART(Elaboratable):
@@ -103,7 +103,7 @@ if __name__ == "__main__":
 
     args = parser.parse_args()
     if args.action == "simulate":
-        from nmigen.sim import Simulator, Passive
+        from amaranth.sim import Simulator, Passive
 
         sim = Simulator(uart)
         sim.add_clock(1e-6)
@@ -141,6 +141,6 @@ if __name__ == "__main__":
             sim.run()
 
     if args.action == "generate":
-        from nmigen.back import verilog
+        from amaranth.back import verilog
 
         print(verilog.convert(uart, ports=ports))

examples/board/01_blinky.py

@@ -1,8 +1,8 @@
-# If the design does not create a "sync" clock domain, it is created by the nMigen build system
+# If the design does not create a "sync" clock domain, it is created by the Amaranth build system
 # using the platform default clock (and default reset, if any).
 
-from nmigen import *
-from nmigen_boards.ice40_hx1k_blink_evn import *
+from amaranth import *
+from amaranth_boards.ice40_hx1k_blink_evn import *
 
 
 class Blinky(Elaboratable):

examples/board/02_domain.py

@@ -2,8 +2,8 @@
 # explicitly, which overrides the default behavior. Any other clock domains could also be
 # independently created in addition to the main "sync" domain.
 
-from nmigen import *
-from nmigen_boards.ice40_hx1k_blink_evn import *
+from amaranth import *
+from amaranth_boards.ice40_hx1k_blink_evn import *
 
 
 class BlinkyWithDomain(Elaboratable):