Rename nMigen to Amaranth HDL.

nmigen/back/__init__.py

@@ -0,0 +1,6 @@
+from amaranth.back import *
+
+
+import warnings
+warnings.warn("instead of nmigen.back, use amaranth.back",
+              DeprecationWarning, stacklevel=2)

nmigen/back/cxxrtl.py

@@ -1,41 +1,7 @@
-from .._toolchain.yosys import *
-from . import rtlil
+from amaranth.back.cxxrtl import *
+from amaranth.back.cxxrtl import __all__
 
 
-__all__ = ["YosysError", "convert", "convert_fragment"]
-
-
-def _convert_rtlil_text(rtlil_text, black_boxes, *, src_loc_at=0):
-    if black_boxes is not None:
-        if not isinstance(black_boxes, dict):
-            raise TypeError("CXXRTL black boxes must be a dictionary, not {!r}"
-                            .format(black_boxes))
-        for box_name, box_source in black_boxes.items():
-            if not isinstance(box_name, str):
-                raise TypeError("CXXRTL black box name must be a string, not {!r}"
-                                .format(box_name))
-            if not isinstance(box_source, str):
-                raise TypeError("CXXRTL black box source code must be a string, not {!r}"
-                                .format(box_source))
-
-    yosys = find_yosys(lambda ver: ver >= (0, 9, 3468))
-
-    script = []
-    if black_boxes is not None:
-        for box_name, box_source in black_boxes.items():
-            script.append("read_ilang <<rtlil\n{}\nrtlil".format(box_source))
-    script.append("read_ilang <<rtlil\n{}\nrtlil".format(rtlil_text))
-    script.append("delete w:$verilog_initial_trigger")
-    script.append("write_cxxrtl")
-
-    return yosys.run(["-q", "-"], "\n".join(script), src_loc_at=1 + src_loc_at)
-
-
-def convert_fragment(*args, black_boxes=None, **kwargs):
-    rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
-    return _convert_rtlil_text(rtlil_text, black_boxes, src_loc_at=1), name_map
-
-
-def convert(*args, black_boxes=None, **kwargs):
-    rtlil_text = rtlil.convert(*args, **kwargs)
-    return _convert_rtlil_text(rtlil_text, black_boxes, src_loc_at=1)
+import warnings
+warnings.warn("instead of nmigen.back.cxxrtl, use amaranth.back.cxxrtl",
+              DeprecationWarning, stacklevel=2)

nmigen/back/pysim.py

@@ -1,11 +1,7 @@
+from amaranth.back.pysim import *
+from amaranth.back.pysim import __all__
+
+
 import warnings
-
-from ..sim import *
-
-
-__all__ = ["Settle", "Delay", "Tick", "Passive", "Active", "Simulator"]
-
-
-# TODO(nmigen-0.4): remove
-warnings.warn("instead of nmigen.back.pysim.*, use nmigen.sim.*",
+warnings.warn("instead of nmigen.back.pysim, use amaranth.back.pysim",
               DeprecationWarning, stacklevel=2)

nmigen/back/verilog.py

@@ -1,61 +1,7 @@
-from .._toolchain.yosys import *
-from . import rtlil
+from amaranth.back.verilog import *
+from amaranth.back.verilog import __all__
 
 
-__all__ = ["YosysError", "convert", "convert_fragment"]
-
-
-def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
-    # this version requirement needs to be synchronized with the one in setup.py!
-    yosys = find_yosys(lambda ver: ver >= (0, 9))
-    yosys_version = yosys.version()
-
-    script = []
-    script.append("read_ilang <<rtlil\n{}\nrtlil".format(rtlil_text))
-
-    if yosys_version >= (0, 9, 3468):
-        # Yosys >=0.9+3468 (since commit 128522f1) emits the workaround for the `always @*`
-        # initial scheduling issue on its own.
-        script.append("delete w:$verilog_initial_trigger")
-
-    if yosys_version >= (0, 9, 3527):
-        # Yosys >=0.9+3527 (since commit 656ee70f) supports the `-nomux` option for the `proc`
-        # script pass. Because the individual `proc_*` passes are not a stable interface,
-        # `proc -nomux` is used instead, if available.
-        script.append("proc -nomux")
-    else:
-        # On earlier versions, use individual `proc_*` passes; this is a known range of Yosys
-        # versions and we know it's compatible with what nMigen does.
-        script.append("proc_init")
-        script.append("proc_arst")
-        script.append("proc_dff")
-        script.append("proc_clean")
-    script.append("memory_collect")
-
-    if strip_internal_attrs:
-        attr_map = []
-        attr_map.append("-remove generator")
-        attr_map.append("-remove top")
-        attr_map.append("-remove src")
-        attr_map.append("-remove nmigen.hierarchy")
-        attr_map.append("-remove nmigen.decoding")
-        script.append("attrmap {}".format(" ".join(attr_map)))
-        script.append("attrmap -modattr {}".format(" ".join(attr_map)))
-
-    script.append("write_verilog -norename {}".format(" ".join(write_verilog_opts)))
-
-    return yosys.run(["-q", "-"], "\n".join(script),
-        # At the moment, Yosys always shows a warning indicating that not all processes can be
-        # translated to Verilog. We carefully emit only the processes that *can* be translated, and
-        # squash this warning. Once Yosys' write_verilog pass is fixed, we should remove this.
-        ignore_warnings=True)
-
-
-def convert_fragment(*args, strip_internal_attrs=False, **kwargs):
-    rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
-    return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs), name_map
-
-
-def convert(*args, strip_internal_attrs=False, **kwargs):
-    rtlil_text = rtlil.convert(*args, **kwargs)
-    return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)
+import warnings
+warnings.warn("instead of nmigen.back.verilog, use amaranth.back.verilog",
+              DeprecationWarning, stacklevel=2)