Rename nMigen to Amaranth HDL.
This commit is contained in:
whitequark
parent
0b28a97ca0
commit
909a3b8be7
200 changed files with 14493 additions and 14451 deletions
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@ -0,0 +1,6 @@
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from amaranth.compat.fhdl import *
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import warnings
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warnings.warn("instead of nmigen.compat.fhdl, use amaranth.compat.fhdl",
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DeprecationWarning, stacklevel=2)
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@ -1,21 +1,7 @@
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from ... import utils
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from ...hdl import ast
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from ..._utils import deprecated
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from amaranth.compat.fhdl.bitcontainer import *
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from amaranth.compat.fhdl.bitcontainer import __all__
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__all__ = ["log2_int", "bits_for", "value_bits_sign"]
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@deprecated("instead of `log2_int`, use `nmigen.utils.log2_int`")
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def log2_int(n, need_pow2=True):
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return utils.log2_int(n, need_pow2)
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@deprecated("instead of `bits_for`, use `nmigen.utils.bits_for`")
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def bits_for(n, require_sign_bit=False):
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return utils.bits_for(n, require_sign_bit)
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@deprecated("instead of `value_bits_sign(v)`, use `v.shape()`")
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def value_bits_sign(v):
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return tuple(ast.Value.cast(v).shape())
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import warnings
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warnings.warn("instead of nmigen.compat.fhdl.bitcontainer, use amaranth.compat.fhdl.bitcontainer",
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DeprecationWarning, stacklevel=2)
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@ -1,35 +1,6 @@
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from operator import itemgetter
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from amaranth.compat.fhdl.conv_output import *
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class ConvOutput:
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def __init__(self):
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self.main_source = ""
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self.data_files = dict()
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def set_main_source(self, src):
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self.main_source = src
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def add_data_file(self, filename_base, content):
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filename = filename_base
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i = 1
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while filename in self.data_files:
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parts = filename_base.split(".", maxsplit=1)
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parts[0] += "_" + str(i)
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filename = ".".join(parts)
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i += 1
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self.data_files[filename] = content
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return filename
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def __str__(self):
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r = self.main_source + "\n"
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for filename, content in sorted(self.data_files.items(),
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key=itemgetter(0)):
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r += filename + ":\n" + content
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return r
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def write(self, main_filename):
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with open(main_filename, "w") as f:
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f.write(self.main_source)
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for filename, content in self.data_files.items():
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with open(filename, "w") as f:
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f.write(content)
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import warnings
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warnings.warn("instead of nmigen.compat.fhdl.conv_output, use amaranth.compat.fhdl.conv_output",
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DeprecationWarning, stacklevel=2)
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@ -1,55 +1,7 @@
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from ...hdl.ast import *
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from ...hdl.xfrm import ResetInserter as NativeResetInserter
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from ...hdl.xfrm import EnableInserter as NativeEnableInserter
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from ...hdl.xfrm import DomainRenamer as NativeDomainRenamer
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from ..._utils import deprecated
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from amaranth.compat.fhdl.decorators import *
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from amaranth.compat.fhdl.decorators import __all__
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__all__ = ["ResetInserter", "CEInserter", "ClockDomainsRenamer"]
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class _CompatControlInserter:
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_control_name = None
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_native_inserter = None
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def __init__(self, clock_domains=None):
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self.clock_domains = clock_domains
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def __call__(self, module):
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if self.clock_domains is None:
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signals = {self._control_name: ("sync", Signal(name=self._control_name))}
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else:
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def name(cd):
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return self._control_name + "_" + cd
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signals = {name(cd): (cd, Signal(name=name(cd))) for cd in self.clock_domains}
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for name, (cd, signal) in signals.items():
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setattr(module, name, signal)
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return self._native_inserter(dict(signals.values()))(module)
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@deprecated("instead of `migen.fhdl.decorators.ResetInserter`, "
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"use `nmigen.hdl.xfrm.ResetInserter`; note that nMigen ResetInserter accepts "
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"a dict of reset signals (or a single reset signal) as an argument, not "
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"a set of clock domain names (or a single clock domain name)")
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class CompatResetInserter(_CompatControlInserter):
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_control_name = "reset"
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_native_inserter = NativeResetInserter
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@deprecated("instead of `migen.fhdl.decorators.CEInserter`, "
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"use `nmigen.hdl.xfrm.EnableInserter`; note that nMigen EnableInserter accepts "
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"a dict of enable signals (or a single enable signal) as an argument, not "
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"a set of clock domain names (or a single clock domain name)")
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class CompatCEInserter(_CompatControlInserter):
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_control_name = "ce"
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_native_inserter = NativeEnableInserter
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class CompatClockDomainsRenamer(NativeDomainRenamer):
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def __init__(self, cd_remapping):
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super().__init__(cd_remapping)
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ResetInserter = CompatResetInserter
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CEInserter = CompatCEInserter
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ClockDomainsRenamer = CompatClockDomainsRenamer
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import warnings
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warnings.warn("instead of nmigen.compat.fhdl.decorators, use amaranth.compat.fhdl.decorators",
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DeprecationWarning, stacklevel=2)
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@ -1,163 +1,7 @@
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from collections.abc import Iterable
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from ..._utils import flatten, deprecated
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from ...hdl import dsl, ir
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from amaranth.compat.fhdl.module import *
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from amaranth.compat.fhdl.module import __all__
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__all__ = ["Module", "FinalizeError"]
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def _flat_list(e):
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if isinstance(e, Iterable):
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return list(flatten(e))
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else:
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return [e]
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class CompatFinalizeError(Exception):
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pass
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FinalizeError = CompatFinalizeError
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class _CompatModuleProxy:
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def __init__(self, cm):
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object.__setattr__(self, "_cm", cm)
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class _CompatModuleComb(_CompatModuleProxy):
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@deprecated("instead of `self.comb +=`, use `m.d.comb +=`")
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def __iadd__(self, assigns):
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self._cm._module._add_statement(assigns, domain=None, depth=0, compat_mode=True)
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return self
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class _CompatModuleSyncCD:
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def __init__(self, cm, cd):
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self._cm = cm
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self._cd = cd
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@deprecated("instead of `self.sync.<domain> +=`, use `m.d.<domain> +=`")
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def __iadd__(self, assigns):
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self._cm._module._add_statement(assigns, domain=self._cd, depth=0, compat_mode=True)
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return self
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class _CompatModuleSync(_CompatModuleProxy):
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@deprecated("instead of `self.sync +=`, use `m.d.sync +=`")
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def __iadd__(self, assigns):
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self._cm._module._add_statement(assigns, domain="sync", depth=0, compat_mode=True)
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return self
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def __getattr__(self, name):
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return _CompatModuleSyncCD(self._cm, name)
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def __setattr__(self, name, value):
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if not isinstance(value, _CompatModuleSyncCD):
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raise AttributeError("Attempted to assign sync property - use += instead")
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class _CompatModuleSpecials(_CompatModuleProxy):
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@deprecated("instead of `self.specials.<name> =`, use `m.submodules.<name> =`")
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def __setattr__(self, name, value):
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self._cm._submodules.append((name, value))
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setattr(self._cm, name, value)
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@deprecated("instead of `self.specials +=`, use `m.submodules +=`")
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def __iadd__(self, other):
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self._cm._submodules += [(None, e) for e in _flat_list(other)]
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return self
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class _CompatModuleSubmodules(_CompatModuleProxy):
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@deprecated("instead of `self.submodules.<name> =`, use `m.submodules.<name> =`")
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def __setattr__(self, name, value):
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self._cm._submodules.append((name, value))
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setattr(self._cm, name, value)
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@deprecated("instead of `self.submodules +=`, use `m.submodules +=`")
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def __iadd__(self, other):
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self._cm._submodules += [(None, e) for e in _flat_list(other)]
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return self
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class _CompatModuleClockDomains(_CompatModuleProxy):
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@deprecated("instead of `self.clock_domains.<name> =`, use `m.domains.<name> =`")
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def __setattr__(self, name, value):
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self.__iadd__(value)
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setattr(self._cm, name, value)
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@deprecated("instead of `self.clock_domains +=`, use `m.domains +=`")
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def __iadd__(self, other):
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self._cm._module.domains += _flat_list(other)
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return self
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class CompatModule(ir.Elaboratable):
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_MustUse__silence = True
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# Actually returns another nMigen Elaboratable (nmigen.dsl.Module), not a Fragment.
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def get_fragment(self):
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assert not self.get_fragment_called
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self.get_fragment_called = True
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self.finalize()
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return self._module
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def elaborate(self, platform):
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if not self.get_fragment_called:
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self.get_fragment()
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return self._module
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def __getattr__(self, name):
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if name == "comb":
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return _CompatModuleComb(self)
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elif name == "sync":
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return _CompatModuleSync(self)
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elif name == "specials":
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return _CompatModuleSpecials(self)
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elif name == "submodules":
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return _CompatModuleSubmodules(self)
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elif name == "clock_domains":
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return _CompatModuleClockDomains(self)
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elif name == "finalized":
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self.finalized = False
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return self.finalized
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elif name == "_module":
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self._module = dsl.Module()
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return self._module
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elif name == "_submodules":
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self._submodules = []
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return self._submodules
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elif name == "_clock_domains":
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self._clock_domains = []
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return self._clock_domains
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elif name == "get_fragment_called":
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self.get_fragment_called = False
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return self.get_fragment_called
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else:
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raise AttributeError("'{}' object has no attribute '{}'"
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.format(type(self).__name__, name))
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def finalize(self, *args, **kwargs):
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def finalize_submodules():
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for name, submodule in self._submodules:
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if not hasattr(submodule, "finalize"):
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continue
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if submodule.finalized:
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continue
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submodule.finalize(*args, **kwargs)
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if not self.finalized:
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self.finalized = True
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finalize_submodules()
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self.do_finalize(*args, **kwargs)
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finalize_submodules()
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for name, submodule in self._submodules:
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self._module._add_submodule(submodule, name)
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def do_finalize(self):
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pass
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Module = CompatModule
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import warnings
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warnings.warn("instead of nmigen.compat.fhdl.module, use amaranth.compat.fhdl.module",
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DeprecationWarning, stacklevel=2)
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@ -1,145 +1,7 @@
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from amaranth.compat.fhdl.specials import *
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from amaranth.compat.fhdl.specials import __all__
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import warnings
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from ..._utils import deprecated, extend
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from ...hdl.ast import *
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from ...hdl.ir import Elaboratable
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from ...hdl.mem import Memory as NativeMemory
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from ...hdl.ir import Fragment, Instance
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from ...hdl.dsl import Module
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from .module import Module as CompatModule
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from .structure import Signal
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from ...lib.io import Pin
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__all__ = ["TSTriple", "Instance", "Memory", "READ_FIRST", "WRITE_FIRST", "NO_CHANGE"]
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class TSTriple:
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def __init__(self, bits_sign=None, min=None, max=None, reset_o=0, reset_oe=0, reset_i=0,
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name=None):
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self.o = Signal(bits_sign, min=min, max=max, reset=reset_o,
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name=None if name is None else name + "_o")
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self.oe = Signal(reset=reset_oe,
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name=None if name is None else name + "_oe")
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self.i = Signal(bits_sign, min=min, max=max, reset=reset_i,
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name=None if name is None else name + "_i")
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def __len__(self):
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return len(self.o)
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def get_tristate(self, io):
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return Tristate(io, self.o, self.oe, self.i)
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class Tristate(Elaboratable):
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def __init__(self, target, o, oe, i=None):
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self.target = target
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self.o = o
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self.oe = oe
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self.i = i if i is not None else None
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def elaborate(self, platform):
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if self.i is None:
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pin = Pin(len(self.target), dir="oe")
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pin.o = self.o
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pin.oe = self.oe
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return platform.get_tristate(pin, self.target, attrs={}, invert=None)
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else:
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pin = Pin(len(self.target), dir="io")
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pin.o = self.o
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pin.oe = self.oe
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pin.i = self.i
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return platform.get_input_output(pin, self.target, attrs={}, invert=None)
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m = Module()
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if self.i is not None:
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m.d.comb += self.i.eq(self.target)
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m.submodules += Instance("$tribuf",
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p_WIDTH=len(self.target),
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i_EN=self.oe,
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i_A=self.o,
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o_Y=self.target,
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)
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f = m.elaborate(platform)
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f.flatten = True
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return f
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(READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
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class _MemoryPort(CompatModule):
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def __init__(self, adr, dat_r, we=None, dat_w=None, async_read=False, re=None,
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we_granularity=0, mode=WRITE_FIRST, clock_domain="sync"):
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self.adr = adr
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self.dat_r = dat_r
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self.we = we
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self.dat_w = dat_w
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self.async_read = async_read
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self.re = re
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self.we_granularity = we_granularity
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self.mode = mode
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self.clock = ClockSignal(clock_domain)
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@extend(NativeMemory)
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@deprecated("it is not necessary or permitted to add Memory as a special or submodule")
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def elaborate(self, platform):
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return Fragment()
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class CompatMemory(NativeMemory, Elaboratable):
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def __init__(self, width, depth, init=None, name=None):
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super().__init__(width=width, depth=depth, init=init, name=name)
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@deprecated("instead of `get_port()`, use `read_port()` and `write_port()`")
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def get_port(self, write_capable=False, async_read=False, has_re=False, we_granularity=0,
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mode=WRITE_FIRST, clock_domain="sync"):
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if we_granularity >= self.width:
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warnings.warn("do not specify `we_granularity` greater than memory width, as it "
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"is a hard error in non-compatibility mode",
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DeprecationWarning, stacklevel=1)
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we_granularity = 0
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if we_granularity == 0:
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warnings.warn("instead of `we_granularity=0`, use `we_granularity=None` or avoid "
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"specifying it at all, as it is a hard error in non-compatibility mode",
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DeprecationWarning, stacklevel=1)
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we_granularity = None
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assert mode != NO_CHANGE
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rdport = self.read_port(domain="comb" if async_read else clock_domain,
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transparent=mode == WRITE_FIRST)
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rdport.addr.name = "{}_addr".format(self.name)
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adr = rdport.addr
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dat_r = rdport.data
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if write_capable:
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wrport = self.write_port(domain=clock_domain, granularity=we_granularity)
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wrport.addr = rdport.addr
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we = wrport.en
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dat_w = wrport.data
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else:
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we = None
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dat_w = None
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if has_re:
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if mode == READ_FIRST:
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re = rdport.en
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else:
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warnings.warn("the combination of `has_re=True` and `mode=WRITE_FIRST` has "
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"surprising behavior: keeping `re` low would merely latch "
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"the address, while the data will change with changing memory "
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"contents; avoid using `re` with transparent ports as it is a hard "
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"error in non-compatibility mode",
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DeprecationWarning, stacklevel=1)
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re = Signal()
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else:
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re = None
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mp = _MemoryPort(adr, dat_r, we, dat_w,
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async_read, re, we_granularity, mode,
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clock_domain)
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mp.submodules.rdport = rdport
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if write_capable:
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mp.submodules.wrport = wrport
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return mp
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Memory = CompatMemory
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warnings.warn("instead of nmigen.compat.fhdl.specials, use amaranth.compat.fhdl.specials",
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DeprecationWarning, stacklevel=2)
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@ -1,185 +1,7 @@
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import builtins
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from amaranth.compat.fhdl.structure import *
|
||||
from amaranth.compat.fhdl.structure import __all__
|
||||
|
||||
|
||||
import warnings
|
||||
from collections import OrderedDict
|
||||
|
||||
from ...utils import bits_for
|
||||
from ..._utils import deprecated, extend
|
||||
from ...hdl import ast
|
||||
from ...hdl.ast import (DUID,
|
||||
Shape, signed, unsigned,
|
||||
Value, Const, C, Mux, Slice as _Slice, Part, Cat, Repl,
|
||||
Signal as NativeSignal,
|
||||
ClockSignal, ResetSignal,
|
||||
Array, ArrayProxy as _ArrayProxy)
|
||||
from ...hdl.cd import ClockDomain
|
||||
|
||||
|
||||
__all__ = ["DUID", "wrap", "Mux", "Cat", "Replicate", "Constant", "C", "Signal", "ClockSignal",
|
||||
"ResetSignal", "If", "Case", "Array", "ClockDomain"]
|
||||
|
||||
|
||||
@deprecated("instead of `wrap`, use `Value.cast`")
|
||||
def wrap(v):
|
||||
return Value.cast(v)
|
||||
|
||||
|
||||
class CompatSignal(NativeSignal):
|
||||
def __init__(self, bits_sign=None, name=None, variable=False, reset=0,
|
||||
reset_less=False, name_override=None, min=None, max=None,
|
||||
related=None, attr=None, src_loc_at=0, **kwargs):
|
||||
if min is not None or max is not None:
|
||||
warnings.warn("instead of `Signal(min={min}, max={max})`, "
|
||||
"use `Signal(range({min}, {max}))`"
|
||||
.format(min=min or 0, max=max or 2),
|
||||
DeprecationWarning, stacklevel=2 + src_loc_at)
|
||||
|
||||
if bits_sign is None:
|
||||
if min is None:
|
||||
min = 0
|
||||
if max is None:
|
||||
max = 2
|
||||
max -= 1 # make both bounds inclusive
|
||||
if min > max:
|
||||
raise ValueError("Lower bound {} should be less or equal to higher bound {}"
|
||||
.format(min, max + 1))
|
||||
sign = min < 0 or max < 0
|
||||
if min == max:
|
||||
bits = 0
|
||||
else:
|
||||
bits = builtins.max(bits_for(min, sign), bits_for(max, sign))
|
||||
shape = signed(bits) if sign else unsigned(bits)
|
||||
else:
|
||||
if not (min is None and max is None):
|
||||
raise ValueError("Only one of bits/signedness or bounds may be specified")
|
||||
shape = bits_sign
|
||||
|
||||
super().__init__(shape=shape, name=name_override or name,
|
||||
reset=reset, reset_less=reset_less,
|
||||
attrs=attr, src_loc_at=1 + src_loc_at, **kwargs)
|
||||
|
||||
|
||||
Signal = CompatSignal
|
||||
|
||||
|
||||
@deprecated("instead of `Constant`, use `Const`")
|
||||
def Constant(value, bits_sign=None):
|
||||
return Const(value, bits_sign)
|
||||
|
||||
|
||||
@deprecated("instead of `Replicate`, use `Repl`")
|
||||
def Replicate(v, n):
|
||||
return Repl(v, n)
|
||||
|
||||
|
||||
@extend(Const)
|
||||
@property
|
||||
@deprecated("instead of `.nbits`, use `.width`")
|
||||
def nbits(self):
|
||||
return self.width
|
||||
|
||||
|
||||
@extend(NativeSignal)
|
||||
@property
|
||||
@deprecated("instead of `.nbits`, use `.width`")
|
||||
def nbits(self):
|
||||
return self.width
|
||||
|
||||
|
||||
@extend(NativeSignal)
|
||||
@NativeSignal.nbits.setter
|
||||
@deprecated("instead of `.nbits = x`, use `.width = x`")
|
||||
def nbits(self, value):
|
||||
self.width = value
|
||||
|
||||
|
||||
@extend(NativeSignal)
|
||||
@deprecated("instead of `.part`, use `.bit_select`")
|
||||
def part(self, offset, width):
|
||||
return Part(self, offset, width, src_loc_at=2)
|
||||
|
||||
|
||||
@extend(Cat)
|
||||
@property
|
||||
@deprecated("instead of `.l`, use `.parts`")
|
||||
def l(self):
|
||||
return self.parts
|
||||
|
||||
|
||||
@extend(ast.Operator)
|
||||
@property
|
||||
@deprecated("instead of `.op`, use `.operator`")
|
||||
def op(self):
|
||||
return self.operator
|
||||
|
||||
|
||||
@extend(_ArrayProxy)
|
||||
@property
|
||||
@deprecated("instead `_ArrayProxy.choices`, use `ArrayProxy.elems`")
|
||||
def choices(self):
|
||||
return self.elems
|
||||
|
||||
|
||||
class If(ast.Switch):
|
||||
@deprecated("instead of `If(cond, ...)`, use `with m.If(cond): ...`")
|
||||
def __init__(self, cond, *stmts):
|
||||
cond = Value.cast(cond)
|
||||
if len(cond) != 1:
|
||||
cond = cond.bool()
|
||||
super().__init__(cond, {("1",): ast.Statement.cast(stmts)})
|
||||
|
||||
@deprecated("instead of `.Elif(cond, ...)`, use `with m.Elif(cond): ...`")
|
||||
def Elif(self, cond, *stmts):
|
||||
cond = Value.cast(cond)
|
||||
if len(cond) != 1:
|
||||
cond = cond.bool()
|
||||
self.cases = OrderedDict((("-" + k,), v) for (k,), v in self.cases.items())
|
||||
self.cases[("1" + "-" * len(self.test),)] = ast.Statement.cast(stmts)
|
||||
self.test = Cat(self.test, cond)
|
||||
return self
|
||||
|
||||
@deprecated("instead of `.Else(...)`, use `with m.Else(): ...`")
|
||||
def Else(self, *stmts):
|
||||
self.cases[()] = ast.Statement.cast(stmts)
|
||||
return self
|
||||
|
||||
|
||||
class Case(ast.Switch):
|
||||
@deprecated("instead of `Case(test, { value: stmts })`, use `with m.Switch(test):` and "
|
||||
"`with m.Case(value): stmts`; instead of `\"default\": stmts`, use "
|
||||
"`with m.Case(): stmts`")
|
||||
def __init__(self, test, cases):
|
||||
new_cases = []
|
||||
default = None
|
||||
for k, v in cases.items():
|
||||
if isinstance(k, (bool, int)):
|
||||
k = Const(k)
|
||||
if (not isinstance(k, Const)
|
||||
and not (isinstance(k, str) and k == "default")):
|
||||
raise TypeError("Case object is not a Migen constant")
|
||||
if isinstance(k, str) and k == "default":
|
||||
default = v
|
||||
continue
|
||||
else:
|
||||
k = k.value
|
||||
new_cases.append((k, v))
|
||||
if default is not None:
|
||||
new_cases.append((None, default))
|
||||
super().__init__(test, OrderedDict(new_cases))
|
||||
|
||||
@deprecated("instead of `Case(...).makedefault()`, use an explicit default case: "
|
||||
"`with m.Case(): ...`")
|
||||
def makedefault(self, key=None):
|
||||
if key is None:
|
||||
for choice in self.cases.keys():
|
||||
if (key is None
|
||||
or (isinstance(choice, str) and choice == "default")
|
||||
or choice > key):
|
||||
key = choice
|
||||
elif isinstance(key, str) and key == "default":
|
||||
key = ()
|
||||
else:
|
||||
key = ("{:0{}b}".format(ast.Value.cast(key).value, len(self.test)),)
|
||||
stmts = self.cases[key]
|
||||
del self.cases[key]
|
||||
self.cases[()] = stmts
|
||||
return self
|
||||
warnings.warn("instead of nmigen.compat.fhdl.structure, use amaranth.compat.fhdl.structure",
|
||||
DeprecationWarning, stacklevel=2)
|
||||
|
|
|
|||
|
|
@ -1,35 +1,6 @@
|
|||
from amaranth.compat.fhdl.verilog import *
|
||||
|
||||
|
||||
import warnings
|
||||
|
||||
from ...hdl.ir import Fragment
|
||||
from ...hdl.cd import ClockDomain
|
||||
from ...back import verilog
|
||||
from .conv_output import ConvOutput
|
||||
from .module import Module
|
||||
|
||||
|
||||
def convert(fi, ios=None, name="top", special_overrides=dict(),
|
||||
attr_translate=None, create_clock_domains=True,
|
||||
display_run=False):
|
||||
if display_run:
|
||||
warnings.warn("`display_run=True` support has been removed",
|
||||
DeprecationWarning, stacklevel=1)
|
||||
if special_overrides:
|
||||
warnings.warn("`special_overrides` support as well as `Special` has been removed",
|
||||
DeprecationWarning, stacklevel=1)
|
||||
# TODO: attr_translate
|
||||
|
||||
if isinstance(fi, Module):
|
||||
fi = fi.get_fragment()
|
||||
|
||||
def missing_domain(name):
|
||||
if create_clock_domains:
|
||||
return ClockDomain(name)
|
||||
v_output = verilog.convert(
|
||||
elaboratable=fi,
|
||||
name=name,
|
||||
ports=ios or (),
|
||||
missing_domain=missing_domain
|
||||
)
|
||||
output = ConvOutput()
|
||||
output.set_main_source(v_output)
|
||||
return output
|
||||
warnings.warn("instead of nmigen.compat.fhdl.verilog, use amaranth.compat.fhdl.verilog",
|
||||
DeprecationWarning, stacklevel=2)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue