Rename nMigen to Amaranth HDL.
This commit is contained in:
whitequark
parent
0b28a97ca0
commit
909a3b8be7
200 changed files with 14493 additions and 14451 deletions
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@ -0,0 +1,6 @@
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from amaranth.lib import *
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import warnings
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warnings.warn("instead of nmigen.lib, use amaranth.lib",
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DeprecationWarning, stacklevel=2)
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@ -1,267 +1,7 @@
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from .. import *
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from amaranth.lib.cdc import *
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from amaranth.lib.cdc import __all__
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__all__ = ["FFSynchronizer", "AsyncFFSynchronizer", "ResetSynchronizer", "PulseSynchronizer"]
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def _check_stages(stages):
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if not isinstance(stages, int) or stages < 1:
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raise TypeError("Synchronization stage count must be a positive integer, not {!r}"
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.format(stages))
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if stages < 2:
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raise ValueError("Synchronization stage count may not safely be less than 2")
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class FFSynchronizer(Elaboratable):
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"""Resynchronise a signal to a different clock domain.
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Consists of a chain of flip-flops. Eliminates metastabilities at the output, but provides
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no other guarantee as to the safe domain-crossing of a signal.
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Parameters
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----------
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i : Signal(n), in
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Signal to be resynchronised.
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o : Signal(n), out
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Signal connected to synchroniser output.
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o_domain : str
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Name of output clock domain.
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reset : int
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Reset value of the flip-flops. On FPGAs, even if ``reset_less`` is True,
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the :class:`FFSynchronizer` is still set to this value during initialization.
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reset_less : bool
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If ``True`` (the default), this :class:`FFSynchronizer` is unaffected by ``o_domain``
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reset. See "Note on Reset" below.
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stages : int
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Number of synchronization stages between input and output. The lowest safe number is 2,
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with higher numbers reducing MTBF further, at the cost of increased latency.
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max_input_delay : None or float
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Maximum delay from the input signal's clock to the first synchronization stage, in seconds.
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If specified and the platform does not support it, elaboration will fail.
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Platform override
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-----------------
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Define the ``get_ff_sync`` platform method to override the implementation of
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:class:`FFSynchronizer`, e.g. to instantiate library cells directly.
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Note on Reset
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-------------
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:class:`FFSynchronizer` is non-resettable by default. Usually this is the safest option;
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on FPGAs the :class:`FFSynchronizer` will still be initialized to its ``reset`` value when
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the FPGA loads its configuration.
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However, in designs where the value of the :class:`FFSynchronizer` must be valid immediately
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after reset, consider setting ``reset_less`` to False if any of the following is true:
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- You are targeting an ASIC, or an FPGA that does not allow arbitrary initial flip-flop states;
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- Your design features warm (non-power-on) resets of ``o_domain``, so the one-time
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initialization at power on is insufficient;
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- Your design features a sequenced reset, and the :class:`FFSynchronizer` must maintain
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its reset value until ``o_domain`` reset specifically is deasserted.
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:class:`FFSynchronizer` is reset by the ``o_domain`` reset only.
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"""
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def __init__(self, i, o, *, o_domain="sync", reset=0, reset_less=True, stages=2,
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max_input_delay=None):
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_check_stages(stages)
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self.i = i
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self.o = o
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self._reset = reset
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self._reset_less = reset_less
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self._o_domain = o_domain
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self._stages = stages
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self._max_input_delay = max_input_delay
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def elaborate(self, platform):
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if hasattr(platform, "get_ff_sync"):
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return platform.get_ff_sync(self)
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if self._max_input_delay is not None:
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raise NotImplementedError("Platform '{}' does not support constraining input delay "
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"for FFSynchronizer"
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.format(type(platform).__name__))
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m = Module()
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flops = [Signal(self.i.shape(), name="stage{}".format(index),
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reset=self._reset, reset_less=self._reset_less)
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for index in range(self._stages)]
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for i, o in zip((self.i, *flops), flops):
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m.d[self._o_domain] += o.eq(i)
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m.d.comb += self.o.eq(flops[-1])
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return m
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class AsyncFFSynchronizer(Elaboratable):
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"""Synchronize deassertion of an asynchronous signal.
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The signal driven by the :class:`AsyncFFSynchronizer` is asserted asynchronously and deasserted
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synchronously, eliminating metastability during deassertion.
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This synchronizer is primarily useful for resets and reset-like signals.
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Parameters
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----------
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i : Signal(1), in
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Asynchronous input signal, to be synchronized.
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o : Signal(1), out
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Synchronously released output signal.
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o_domain : str
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Name of clock domain to synchronize to.
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stages : int, >=2
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Number of synchronization stages between input and output. The lowest safe number is 2,
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with higher numbers reducing MTBF further, at the cost of increased deassertion latency.
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async_edge : str
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The edge of the input signal which causes the output to be set. Must be one of "pos" or "neg".
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max_input_delay : None or float
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Maximum delay from the input signal's clock to the first synchronization stage, in seconds.
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If specified and the platform does not support it, elaboration will fail.
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Platform override
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-----------------
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Define the ``get_async_ff_sync`` platform method to override the implementation of
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:class:`AsyncFFSynchronizer`, e.g. to instantiate library cells directly.
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"""
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def __init__(self, i, o, *, o_domain="sync", stages=2, async_edge="pos", max_input_delay=None):
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_check_stages(stages)
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if len(i) != 1:
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raise ValueError("AsyncFFSynchronizer input width must be 1, not {}"
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.format(len(i)))
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if len(o) != 1:
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raise ValueError("AsyncFFSynchronizer output width must be 1, not {}"
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.format(len(o)))
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if async_edge not in ("pos", "neg"):
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raise ValueError("AsyncFFSynchronizer async edge must be one of 'pos' or 'neg', "
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"not {!r}"
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.format(async_edge))
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self.i = i
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self.o = o
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self._o_domain = o_domain
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self._stages = stages
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self._edge = async_edge
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self._max_input_delay = max_input_delay
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def elaborate(self, platform):
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if hasattr(platform, "get_async_ff_sync"):
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return platform.get_async_ff_sync(self)
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if self._max_input_delay is not None:
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raise NotImplementedError("Platform '{}' does not support constraining input delay "
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"for AsyncFFSynchronizer"
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.format(type(platform).__name__))
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m = Module()
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m.domains += ClockDomain("async_ff", async_reset=True, local=True)
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flops = [Signal(1, name="stage{}".format(index), reset=1)
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for index in range(self._stages)]
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for i, o in zip((0, *flops), flops):
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m.d.async_ff += o.eq(i)
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if self._edge == "pos":
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m.d.comb += ResetSignal("async_ff").eq(self.i)
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else:
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m.d.comb += ResetSignal("async_ff").eq(~self.i)
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m.d.comb += [
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ClockSignal("async_ff").eq(ClockSignal(self._o_domain)),
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self.o.eq(flops[-1])
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]
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return m
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class ResetSynchronizer(Elaboratable):
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"""Synchronize deassertion of a clock domain reset.
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The reset of the clock domain driven by the :class:`ResetSynchronizer` is asserted
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asynchronously and deasserted synchronously, eliminating metastability during deassertion.
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The driven clock domain could use a reset that is asserted either synchronously or
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asynchronously; a reset is always deasserted synchronously. A domain with an asynchronously
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asserted reset is useful if the clock of the domain may be gated, yet the domain still
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needs to be reset promptly; otherwise, synchronously asserted reset (the default) should
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be used.
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Parameters
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----------
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arst : Signal(1), in
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Asynchronous reset signal, to be synchronized.
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domain : str
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Name of clock domain to reset.
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stages : int, >=2
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Number of synchronization stages between input and output. The lowest safe number is 2,
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with higher numbers reducing MTBF further, at the cost of increased deassertion latency.
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max_input_delay : None or float
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Maximum delay from the input signal's clock to the first synchronization stage, in seconds.
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If specified and the platform does not support it, elaboration will fail.
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Platform override
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-----------------
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Define the ``get_reset_sync`` platform method to override the implementation of
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:class:`ResetSynchronizer`, e.g. to instantiate library cells directly.
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"""
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def __init__(self, arst, *, domain="sync", stages=2, max_input_delay=None):
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_check_stages(stages)
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self.arst = arst
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self._domain = domain
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self._stages = stages
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self._max_input_delay = max_input_delay
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def elaborate(self, platform):
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return AsyncFFSynchronizer(self.arst, ResetSignal(self._domain), o_domain=self._domain,
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stages=self._stages, max_input_delay=self._max_input_delay)
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class PulseSynchronizer(Elaboratable):
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"""A one-clock pulse on the input produces a one-clock pulse on the output.
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If the output clock is faster than the input clock, then the input may be safely asserted at
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100% duty cycle. Otherwise, if the clock ratio is `n`:1, the input may be asserted at most once
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in every `n` input clocks, else pulses may be dropped. Other than this there is no constraint
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on the ratio of input and output clock frequency.
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Parameters
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----------
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i_domain : str
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Name of input clock domain.
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o_domain : str
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Name of output clock domain.
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stages : int, >=2
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Number of synchronization stages between input and output. The lowest safe number is 2,
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with higher numbers reducing MTBF further, at the cost of increased deassertion latency.
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"""
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def __init__(self, i_domain, o_domain, *, stages=2):
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_check_stages(stages)
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self.i = Signal()
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self.o = Signal()
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self._i_domain = i_domain
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self._o_domain = o_domain
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self._stages = stages
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def elaborate(self, platform):
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m = Module()
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i_toggle = Signal()
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o_toggle = Signal()
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r_toggle = Signal()
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ff_sync = m.submodules.ff_sync = \
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FFSynchronizer(i_toggle, o_toggle, o_domain=self._o_domain, stages=self._stages)
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m.d[self._i_domain] += i_toggle.eq(i_toggle ^ self.i)
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m.d[self._o_domain] += r_toggle.eq(o_toggle)
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m.d.comb += self.o.eq(o_toggle ^ r_toggle)
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return m
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import warnings
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warnings.warn("instead of nmigen.lib.cdc, use amaranth.lib.cdc",
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DeprecationWarning, stacklevel=2)
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@ -1,186 +1,7 @@
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"""Encoders and decoders between binary and one-hot representation."""
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from .. import *
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from amaranth.lib.coding import *
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from amaranth.lib.coding import __all__
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__all__ = [
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"Encoder", "Decoder",
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"PriorityEncoder", "PriorityDecoder",
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"GrayEncoder", "GrayDecoder",
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]
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class Encoder(Elaboratable):
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"""Encode one-hot to binary.
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If one bit in ``i`` is asserted, ``n`` is low and ``o`` indicates the asserted bit.
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Otherwise, ``n`` is high and ``o`` is ``0``.
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Parameters
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----------
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width : int
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Bit width of the input
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Attributes
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----------
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i : Signal(width), in
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One-hot input.
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o : Signal(range(width)), out
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Encoded binary.
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n : Signal, out
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Invalid: either none or multiple input bits are asserted.
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"""
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def __init__(self, width):
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self.width = width
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self.i = Signal(width)
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self.o = Signal(range(width))
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self.n = Signal()
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def elaborate(self, platform):
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m = Module()
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with m.Switch(self.i):
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for j in range(self.width):
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with m.Case(1 << j):
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m.d.comb += self.o.eq(j)
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with m.Case():
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m.d.comb += self.n.eq(1)
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return m
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class PriorityEncoder(Elaboratable):
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"""Priority encode requests to binary.
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If any bit in ``i`` is asserted, ``n`` is low and ``o`` indicates the least significant
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asserted bit.
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Otherwise, ``n`` is high and ``o`` is ``0``.
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Parameters
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----------
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width : int
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Bit width of the input.
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Attributes
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----------
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i : Signal(width), in
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Input requests.
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o : Signal(range(width)), out
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Encoded binary.
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n : Signal, out
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Invalid: no input bits are asserted.
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"""
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def __init__(self, width):
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self.width = width
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self.i = Signal(width)
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self.o = Signal(range(width))
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self.n = Signal()
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def elaborate(self, platform):
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m = Module()
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for j in reversed(range(self.width)):
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with m.If(self.i[j]):
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m.d.comb += self.o.eq(j)
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m.d.comb += self.n.eq(self.i == 0)
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return m
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class Decoder(Elaboratable):
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"""Decode binary to one-hot.
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If ``n`` is low, only the ``i``th bit in ``o`` is asserted.
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If ``n`` is high, ``o`` is ``0``.
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Parameters
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----------
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width : int
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Bit width of the output.
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Attributes
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----------
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i : Signal(range(width)), in
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Input binary.
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o : Signal(width), out
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Decoded one-hot.
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n : Signal, in
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Invalid, no output bits are to be asserted.
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"""
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def __init__(self, width):
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self.width = width
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self.i = Signal(range(width))
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self.n = Signal()
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self.o = Signal(width)
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def elaborate(self, platform):
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m = Module()
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with m.Switch(self.i):
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for j in range(len(self.o)):
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with m.Case(j):
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m.d.comb += self.o.eq(1 << j)
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with m.If(self.n):
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m.d.comb += self.o.eq(0)
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return m
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class PriorityDecoder(Decoder):
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"""Decode binary to priority request.
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Identical to :class:`Decoder`.
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"""
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class GrayEncoder(Elaboratable):
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"""Encode binary to Gray code.
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Parameters
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----------
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width : int
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Bit width.
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Attributes
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----------
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i : Signal(width), in
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Input natural binary.
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o : Signal(width), out
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Encoded Gray code.
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"""
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def __init__(self, width):
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self.width = width
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self.i = Signal(width)
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self.o = Signal(width)
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def elaborate(self, platform):
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m = Module()
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m.d.comb += self.o.eq(self.i ^ self.i[1:])
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return m
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class GrayDecoder(Elaboratable):
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"""Decode Gray code to binary.
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Parameters
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----------
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width : int
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Bit width.
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Attributes
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----------
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i : Signal(width), in
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Input Gray code.
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o : Signal(width), out
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Decoded natural binary.
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"""
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def __init__(self, width):
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self.width = width
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self.i = Signal(width)
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self.o = Signal(width)
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def elaborate(self, platform):
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m = Module()
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m.d.comb += self.o[-1].eq(self.i[-1])
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for i in reversed(range(self.width - 1)):
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m.d.comb += self.o[i].eq(self.o[i + 1] ^ self.i[i])
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return m
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import warnings
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warnings.warn("instead of nmigen.lib.coding, use amaranth.lib.coding",
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DeprecationWarning, stacklevel=2)
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@ -1,529 +1,7 @@
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"""First-in first-out queues."""
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from amaranth.lib.fifo import *
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from amaranth.lib.fifo import __all__
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from .. import *
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from ..asserts import *
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from .._utils import log2_int
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from .coding import GrayEncoder, GrayDecoder
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from .cdc import FFSynchronizer, AsyncFFSynchronizer
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__all__ = ["FIFOInterface", "SyncFIFO", "SyncFIFOBuffered", "AsyncFIFO", "AsyncFIFOBuffered"]
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class FIFOInterface:
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_doc_template = """
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{description}
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Parameters
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----------
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width : int
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Bit width of data entries.
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depth : int
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Depth of the queue. If zero, the FIFO cannot be read from or written to.
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{parameters}
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Attributes
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----------
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||||
{attributes}
|
||||
w_data : in, width
|
||||
Input data.
|
||||
w_rdy : out
|
||||
Asserted if there is space in the queue, i.e. ``w_en`` can be asserted to write
|
||||
a new entry.
|
||||
w_en : in
|
||||
Write strobe. Latches ``w_data`` into the queue. Does nothing if ``w_rdy`` is not asserted.
|
||||
w_level : out
|
||||
Number of unread entries.
|
||||
{w_attributes}
|
||||
r_data : out, width
|
||||
Output data. {r_data_valid}
|
||||
r_rdy : out
|
||||
Asserted if there is an entry in the queue, i.e. ``r_en`` can be asserted to read
|
||||
an existing entry.
|
||||
r_en : in
|
||||
Read strobe. Makes the next entry (if any) available on ``r_data`` at the next cycle.
|
||||
Does nothing if ``r_rdy`` is not asserted.
|
||||
r_level : out
|
||||
Number of unread entries.
|
||||
{r_attributes}
|
||||
"""
|
||||
|
||||
__doc__ = _doc_template.format(description="""
|
||||
Data written to the input interface (``w_data``, ``w_rdy``, ``w_en``) is buffered and can be
|
||||
read at the output interface (``r_data``, ``r_rdy``, ``r_en`). The data entry written first
|
||||
to the input also appears first on the output.
|
||||
""",
|
||||
parameters="",
|
||||
r_data_valid="The conditions in which ``r_data`` is valid depends on the type of the queue.",
|
||||
attributes="""
|
||||
fwft : bool
|
||||
First-word fallthrough. If set, when ``r_rdy`` rises, the first entry is already
|
||||
available, i.e. ``r_data`` is valid. Otherwise, after ``r_rdy`` rises, it is necessary
|
||||
to strobe ``r_en`` for ``r_data`` to become valid.
|
||||
""".strip(),
|
||||
w_attributes="",
|
||||
r_attributes="")
|
||||
|
||||
def __init__(self, *, width, depth, fwft):
|
||||
if not isinstance(width, int) or width < 0:
|
||||
raise TypeError("FIFO width must be a non-negative integer, not {!r}"
|
||||
.format(width))
|
||||
if not isinstance(depth, int) or depth < 0:
|
||||
raise TypeError("FIFO depth must be a non-negative integer, not {!r}"
|
||||
.format(depth))
|
||||
self.width = width
|
||||
self.depth = depth
|
||||
self.fwft = fwft
|
||||
|
||||
self.w_data = Signal(width, reset_less=True)
|
||||
self.w_rdy = Signal() # writable; not full
|
||||
self.w_en = Signal()
|
||||
self.w_level = Signal(range(depth + 1))
|
||||
|
||||
self.r_data = Signal(width, reset_less=True)
|
||||
self.r_rdy = Signal() # readable; not empty
|
||||
self.r_en = Signal()
|
||||
self.r_level = Signal(range(depth + 1))
|
||||
|
||||
|
||||
def _incr(signal, modulo):
|
||||
if modulo == 2 ** len(signal):
|
||||
return signal + 1
|
||||
else:
|
||||
return Mux(signal == modulo - 1, 0, signal + 1)
|
||||
|
||||
|
||||
class SyncFIFO(Elaboratable, FIFOInterface):
|
||||
__doc__ = FIFOInterface._doc_template.format(
|
||||
description="""
|
||||
Synchronous first in, first out queue.
|
||||
|
||||
Read and write interfaces are accessed from the same clock domain. If different clock domains
|
||||
are needed, use :class:`AsyncFIFO`.
|
||||
""".strip(),
|
||||
parameters="""
|
||||
fwft : bool
|
||||
First-word fallthrough. If set, when the queue is empty and an entry is written into it,
|
||||
that entry becomes available on the output on the same clock cycle. Otherwise, it is
|
||||
necessary to assert ``r_en`` for ``r_data`` to become valid.
|
||||
""".strip(),
|
||||
r_data_valid="""
|
||||
For FWFT queues, valid if ``r_rdy`` is asserted. For non-FWFT queues, valid on the next
|
||||
cycle after ``r_rdy`` and ``r_en`` have been asserted.
|
||||
""".strip(),
|
||||
attributes="",
|
||||
r_attributes="",
|
||||
w_attributes="")
|
||||
|
||||
def __init__(self, *, width, depth, fwft=True):
|
||||
super().__init__(width=width, depth=depth, fwft=fwft)
|
||||
|
||||
self.level = Signal(range(depth + 1))
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
if self.depth == 0:
|
||||
m.d.comb += [
|
||||
self.w_rdy.eq(0),
|
||||
self.r_rdy.eq(0),
|
||||
]
|
||||
return m
|
||||
|
||||
m.d.comb += [
|
||||
self.w_rdy.eq(self.level != self.depth),
|
||||
self.r_rdy.eq(self.level != 0),
|
||||
self.w_level.eq(self.level),
|
||||
self.r_level.eq(self.level),
|
||||
]
|
||||
|
||||
do_read = self.r_rdy & self.r_en
|
||||
do_write = self.w_rdy & self.w_en
|
||||
|
||||
storage = Memory(width=self.width, depth=self.depth)
|
||||
w_port = m.submodules.w_port = storage.write_port()
|
||||
r_port = m.submodules.r_port = storage.read_port(
|
||||
domain="comb" if self.fwft else "sync", transparent=self.fwft)
|
||||
produce = Signal(range(self.depth))
|
||||
consume = Signal(range(self.depth))
|
||||
|
||||
m.d.comb += [
|
||||
w_port.addr.eq(produce),
|
||||
w_port.data.eq(self.w_data),
|
||||
w_port.en.eq(self.w_en & self.w_rdy),
|
||||
]
|
||||
with m.If(do_write):
|
||||
m.d.sync += produce.eq(_incr(produce, self.depth))
|
||||
|
||||
m.d.comb += [
|
||||
r_port.addr.eq(consume),
|
||||
self.r_data.eq(r_port.data),
|
||||
]
|
||||
if not self.fwft:
|
||||
m.d.comb += r_port.en.eq(self.r_en)
|
||||
with m.If(do_read):
|
||||
m.d.sync += consume.eq(_incr(consume, self.depth))
|
||||
|
||||
with m.If(do_write & ~do_read):
|
||||
m.d.sync += self.level.eq(self.level + 1)
|
||||
with m.If(do_read & ~do_write):
|
||||
m.d.sync += self.level.eq(self.level - 1)
|
||||
|
||||
if platform == "formal":
|
||||
# TODO: move this logic to SymbiYosys
|
||||
with m.If(Initial()):
|
||||
m.d.comb += [
|
||||
Assume(produce < self.depth),
|
||||
Assume(consume < self.depth),
|
||||
]
|
||||
with m.If(produce == consume):
|
||||
m.d.comb += Assume((self.level == 0) | (self.level == self.depth))
|
||||
with m.If(produce > consume):
|
||||
m.d.comb += Assume(self.level == (produce - consume))
|
||||
with m.If(produce < consume):
|
||||
m.d.comb += Assume(self.level == (self.depth + produce - consume))
|
||||
with m.Else():
|
||||
m.d.comb += [
|
||||
Assert(produce < self.depth),
|
||||
Assert(consume < self.depth),
|
||||
]
|
||||
with m.If(produce == consume):
|
||||
m.d.comb += Assert((self.level == 0) | (self.level == self.depth))
|
||||
with m.If(produce > consume):
|
||||
m.d.comb += Assert(self.level == (produce - consume))
|
||||
with m.If(produce < consume):
|
||||
m.d.comb += Assert(self.level == (self.depth + produce - consume))
|
||||
|
||||
return m
|
||||
|
||||
|
||||
class SyncFIFOBuffered(Elaboratable, FIFOInterface):
|
||||
__doc__ = FIFOInterface._doc_template.format(
|
||||
description="""
|
||||
Buffered synchronous first in, first out queue.
|
||||
|
||||
This queue's interface is identical to :class:`SyncFIFO` configured as ``fwft=True``, but it
|
||||
does not use asynchronous memory reads, which are incompatible with FPGA block RAMs.
|
||||
|
||||
In exchange, the latency between an entry being written to an empty queue and that entry
|
||||
becoming available on the output is increased by one cycle compared to :class:`SyncFIFO`.
|
||||
""".strip(),
|
||||
parameters="""
|
||||
fwft : bool
|
||||
Always set.
|
||||
""".strip(),
|
||||
attributes="",
|
||||
r_data_valid="Valid if ``r_rdy`` is asserted.",
|
||||
r_attributes="""
|
||||
level : out
|
||||
Number of unread entries.
|
||||
""".strip(),
|
||||
w_attributes="")
|
||||
|
||||
def __init__(self, *, width, depth):
|
||||
super().__init__(width=width, depth=depth, fwft=True)
|
||||
|
||||
self.level = Signal(range(depth + 1))
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
if self.depth == 0:
|
||||
m.d.comb += [
|
||||
self.w_rdy.eq(0),
|
||||
self.r_rdy.eq(0),
|
||||
]
|
||||
return m
|
||||
|
||||
# Effectively, this queue treats the output register of the non-FWFT inner queue as
|
||||
# an additional storage element.
|
||||
m.submodules.unbuffered = fifo = SyncFIFO(width=self.width, depth=self.depth - 1,
|
||||
fwft=False)
|
||||
|
||||
m.d.comb += [
|
||||
fifo.w_data.eq(self.w_data),
|
||||
fifo.w_en.eq(self.w_en),
|
||||
self.w_rdy.eq(fifo.w_rdy),
|
||||
]
|
||||
|
||||
m.d.comb += [
|
||||
self.r_data.eq(fifo.r_data),
|
||||
fifo.r_en.eq(fifo.r_rdy & (~self.r_rdy | self.r_en)),
|
||||
]
|
||||
with m.If(fifo.r_en):
|
||||
m.d.sync += self.r_rdy.eq(1)
|
||||
with m.Elif(self.r_en):
|
||||
m.d.sync += self.r_rdy.eq(0)
|
||||
|
||||
m.d.comb += [
|
||||
self.level.eq(fifo.level + self.r_rdy),
|
||||
self.w_level.eq(self.level),
|
||||
self.r_level.eq(self.level),
|
||||
]
|
||||
|
||||
return m
|
||||
|
||||
|
||||
class AsyncFIFO(Elaboratable, FIFOInterface):
|
||||
__doc__ = FIFOInterface._doc_template.format(
|
||||
description="""
|
||||
Asynchronous first in, first out queue.
|
||||
|
||||
Read and write interfaces are accessed from different clock domains, which can be set when
|
||||
constructing the FIFO.
|
||||
|
||||
:class:`AsyncFIFO` can be reset from the write clock domain. When the write domain reset is
|
||||
asserted, the FIFO becomes empty. When the read domain is reset, data remains in the FIFO - the
|
||||
read domain logic should correctly handle this case.
|
||||
|
||||
:class:`AsyncFIFO` only supports power of 2 depths. Unless ``exact_depth`` is specified,
|
||||
the ``depth`` parameter is rounded up to the next power of 2.
|
||||
""".strip(),
|
||||
parameters="""
|
||||
r_domain : str
|
||||
Read clock domain.
|
||||
w_domain : str
|
||||
Write clock domain.
|
||||
""".strip(),
|
||||
attributes="""
|
||||
fwft : bool
|
||||
Always set.
|
||||
""".strip(),
|
||||
r_data_valid="Valid if ``r_rdy`` is asserted.",
|
||||
r_attributes="""
|
||||
r_rst : Signal, out
|
||||
Asserted while the FIFO is being reset by the write-domain reset (for at least one
|
||||
read-domain clock cycle).
|
||||
""".strip(),
|
||||
w_attributes="")
|
||||
|
||||
def __init__(self, *, width, depth, r_domain="read", w_domain="write", exact_depth=False):
|
||||
if depth != 0:
|
||||
try:
|
||||
depth_bits = log2_int(depth, need_pow2=exact_depth)
|
||||
depth = 1 << depth_bits
|
||||
except ValueError:
|
||||
raise ValueError("AsyncFIFO only supports depths that are powers of 2; requested "
|
||||
"exact depth {} is not"
|
||||
.format(depth)) from None
|
||||
else:
|
||||
depth_bits = 0
|
||||
super().__init__(width=width, depth=depth, fwft=True)
|
||||
|
||||
self.r_rst = Signal()
|
||||
self._r_domain = r_domain
|
||||
self._w_domain = w_domain
|
||||
self._ctr_bits = depth_bits + 1
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
if self.depth == 0:
|
||||
m.d.comb += [
|
||||
self.w_rdy.eq(0),
|
||||
self.r_rdy.eq(0),
|
||||
]
|
||||
return m
|
||||
|
||||
# The design of this queue is the "style #2" from Clifford E. Cummings' paper "Simulation
|
||||
# and Synthesis Techniques for Asynchronous FIFO Design":
|
||||
# http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
|
||||
|
||||
do_write = self.w_rdy & self.w_en
|
||||
do_read = self.r_rdy & self.r_en
|
||||
|
||||
# TODO: extract this pattern into lib.cdc.GrayCounter
|
||||
produce_w_bin = Signal(self._ctr_bits)
|
||||
produce_w_nxt = Signal(self._ctr_bits)
|
||||
m.d.comb += produce_w_nxt.eq(produce_w_bin + do_write)
|
||||
m.d[self._w_domain] += produce_w_bin.eq(produce_w_nxt)
|
||||
|
||||
# Note: Both read-domain counters must be reset_less (see comments below)
|
||||
consume_r_bin = Signal(self._ctr_bits, reset_less=True)
|
||||
consume_r_nxt = Signal(self._ctr_bits)
|
||||
m.d.comb += consume_r_nxt.eq(consume_r_bin + do_read)
|
||||
m.d[self._r_domain] += consume_r_bin.eq(consume_r_nxt)
|
||||
|
||||
produce_w_gry = Signal(self._ctr_bits)
|
||||
produce_r_gry = Signal(self._ctr_bits)
|
||||
produce_enc = m.submodules.produce_enc = \
|
||||
GrayEncoder(self._ctr_bits)
|
||||
produce_cdc = m.submodules.produce_cdc = \
|
||||
FFSynchronizer(produce_w_gry, produce_r_gry, o_domain=self._r_domain)
|
||||
m.d.comb += produce_enc.i.eq(produce_w_nxt),
|
||||
m.d[self._w_domain] += produce_w_gry.eq(produce_enc.o)
|
||||
|
||||
consume_r_gry = Signal(self._ctr_bits, reset_less=True)
|
||||
consume_w_gry = Signal(self._ctr_bits)
|
||||
consume_enc = m.submodules.consume_enc = \
|
||||
GrayEncoder(self._ctr_bits)
|
||||
consume_cdc = m.submodules.consume_cdc = \
|
||||
FFSynchronizer(consume_r_gry, consume_w_gry, o_domain=self._w_domain)
|
||||
m.d.comb += consume_enc.i.eq(consume_r_nxt)
|
||||
m.d[self._r_domain] += consume_r_gry.eq(consume_enc.o)
|
||||
|
||||
consume_w_bin = Signal(self._ctr_bits)
|
||||
consume_dec = m.submodules.consume_dec = \
|
||||
GrayDecoder(self._ctr_bits)
|
||||
m.d.comb += consume_dec.i.eq(consume_w_gry),
|
||||
m.d[self._w_domain] += consume_w_bin.eq(consume_dec.o)
|
||||
|
||||
produce_r_bin = Signal(self._ctr_bits)
|
||||
produce_dec = m.submodules.produce_dec = \
|
||||
GrayDecoder(self._ctr_bits)
|
||||
m.d.comb += produce_dec.i.eq(produce_r_gry),
|
||||
m.d.comb += produce_r_bin.eq(produce_dec.o)
|
||||
|
||||
w_full = Signal()
|
||||
r_empty = Signal()
|
||||
m.d.comb += [
|
||||
w_full.eq((produce_w_gry[-1] != consume_w_gry[-1]) &
|
||||
(produce_w_gry[-2] != consume_w_gry[-2]) &
|
||||
(produce_w_gry[:-2] == consume_w_gry[:-2])),
|
||||
r_empty.eq(consume_r_gry == produce_r_gry),
|
||||
]
|
||||
|
||||
m.d[self._w_domain] += self.w_level.eq((produce_w_bin - consume_w_bin))
|
||||
m.d.comb += self.r_level.eq((produce_r_bin - consume_r_bin))
|
||||
|
||||
storage = Memory(width=self.width, depth=self.depth)
|
||||
w_port = m.submodules.w_port = storage.write_port(domain=self._w_domain)
|
||||
r_port = m.submodules.r_port = storage.read_port (domain=self._r_domain,
|
||||
transparent=False)
|
||||
m.d.comb += [
|
||||
w_port.addr.eq(produce_w_bin[:-1]),
|
||||
w_port.data.eq(self.w_data),
|
||||
w_port.en.eq(do_write),
|
||||
self.w_rdy.eq(~w_full),
|
||||
]
|
||||
m.d.comb += [
|
||||
r_port.addr.eq(consume_r_nxt[:-1]),
|
||||
self.r_data.eq(r_port.data),
|
||||
r_port.en.eq(1),
|
||||
self.r_rdy.eq(~r_empty),
|
||||
]
|
||||
|
||||
# Reset handling to maintain FIFO and CDC invariants in the presence of a write-domain
|
||||
# reset.
|
||||
# There is a CDC hazard associated with resetting an async FIFO - Gray code counters which
|
||||
# are reset to 0 violate their Gray code invariant. One way to handle this is to ensure
|
||||
# that both sides of the FIFO are asynchronously reset by the same signal. We adopt a
|
||||
# slight variation on this approach - reset control rests entirely with the write domain.
|
||||
# The write domain's reset signal is used to asynchronously reset the read domain's
|
||||
# counters and force the FIFO to be empty when the write domain's reset is asserted.
|
||||
# This requires the two read domain counters to be marked as "reset_less", as they are
|
||||
# reset through another mechanism. See https://github.com/nmigen/nmigen/issues/181 for the
|
||||
# full discussion.
|
||||
w_rst = ResetSignal(domain=self._w_domain, allow_reset_less=True)
|
||||
r_rst = Signal()
|
||||
|
||||
# Async-set-sync-release synchronizer avoids CDC hazards
|
||||
rst_cdc = m.submodules.rst_cdc = \
|
||||
AsyncFFSynchronizer(w_rst, r_rst, o_domain=self._r_domain)
|
||||
|
||||
# Decode Gray code counter synchronized from write domain to overwrite binary
|
||||
# counter in read domain.
|
||||
rst_dec = m.submodules.rst_dec = \
|
||||
GrayDecoder(self._ctr_bits)
|
||||
m.d.comb += rst_dec.i.eq(produce_r_gry)
|
||||
with m.If(r_rst):
|
||||
m.d.comb += r_empty.eq(1)
|
||||
m.d[self._r_domain] += consume_r_gry.eq(produce_r_gry)
|
||||
m.d[self._r_domain] += consume_r_bin.eq(rst_dec.o)
|
||||
m.d[self._r_domain] += self.r_rst.eq(1)
|
||||
with m.Else():
|
||||
m.d[self._r_domain] += self.r_rst.eq(0)
|
||||
|
||||
if platform == "formal":
|
||||
with m.If(Initial()):
|
||||
m.d.comb += Assume(produce_w_gry == (produce_w_bin ^ produce_w_bin[1:]))
|
||||
m.d.comb += Assume(consume_r_gry == (consume_r_bin ^ consume_r_bin[1:]))
|
||||
|
||||
return m
|
||||
|
||||
|
||||
class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
|
||||
__doc__ = FIFOInterface._doc_template.format(
|
||||
description="""
|
||||
Buffered asynchronous first in, first out queue.
|
||||
|
||||
Read and write interfaces are accessed from different clock domains, which can be set when
|
||||
constructing the FIFO.
|
||||
|
||||
:class:`AsyncFIFOBuffered` only supports power of 2 plus one depths. Unless ``exact_depth``
|
||||
is specified, the ``depth`` parameter is rounded up to the next power of 2 plus one.
|
||||
(The output buffer acts as an additional queue element.)
|
||||
|
||||
This queue's interface is identical to :class:`AsyncFIFO`, but it has an additional register
|
||||
on the output, improving timing in case of block RAM that has large clock-to-output delay.
|
||||
|
||||
In exchange, the latency between an entry being written to an empty queue and that entry
|
||||
becoming available on the output is increased by one cycle compared to :class:`AsyncFIFO`.
|
||||
""".strip(),
|
||||
parameters="""
|
||||
r_domain : str
|
||||
Read clock domain.
|
||||
w_domain : str
|
||||
Write clock domain.
|
||||
""".strip(),
|
||||
attributes="""
|
||||
fwft : bool
|
||||
Always set.
|
||||
""".strip(),
|
||||
r_data_valid="Valid if ``r_rdy`` is asserted.",
|
||||
r_attributes="""
|
||||
r_rst : Signal, out
|
||||
Asserted while the FIFO is being reset by the write-domain reset (for at least one
|
||||
read-domain clock cycle).
|
||||
""".strip(),
|
||||
w_attributes="")
|
||||
|
||||
def __init__(self, *, width, depth, r_domain="read", w_domain="write", exact_depth=False):
|
||||
if depth != 0:
|
||||
try:
|
||||
depth_bits = log2_int(max(0, depth - 1), need_pow2=exact_depth)
|
||||
depth = (1 << depth_bits) + 1
|
||||
except ValueError:
|
||||
raise ValueError("AsyncFIFOBuffered only supports depths that are one higher "
|
||||
"than powers of 2; requested exact depth {} is not"
|
||||
.format(depth)) from None
|
||||
super().__init__(width=width, depth=depth, fwft=True)
|
||||
|
||||
self.r_rst = Signal()
|
||||
self._r_domain = r_domain
|
||||
self._w_domain = w_domain
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
if self.depth == 0:
|
||||
m.d.comb += [
|
||||
self.w_rdy.eq(0),
|
||||
self.r_rdy.eq(0),
|
||||
]
|
||||
return m
|
||||
|
||||
m.submodules.unbuffered = fifo = AsyncFIFO(width=self.width, depth=self.depth - 1,
|
||||
r_domain=self._r_domain, w_domain=self._w_domain)
|
||||
|
||||
m.d.comb += [
|
||||
fifo.w_data.eq(self.w_data),
|
||||
self.w_rdy.eq(fifo.w_rdy),
|
||||
fifo.w_en.eq(self.w_en),
|
||||
]
|
||||
|
||||
r_consume_buffered = Signal()
|
||||
m.d.comb += r_consume_buffered.eq((self.r_rdy - self.r_en) & self.r_rdy)
|
||||
m.d[self._r_domain] += self.r_level.eq(fifo.r_level + r_consume_buffered)
|
||||
|
||||
w_consume_buffered = Signal()
|
||||
m.submodules.consume_buffered_cdc = FFSynchronizer(r_consume_buffered, w_consume_buffered, o_domain=self._w_domain, stages=4)
|
||||
m.d.comb += self.w_level.eq(fifo.w_level + w_consume_buffered)
|
||||
|
||||
with m.If(self.r_en | ~self.r_rdy):
|
||||
m.d[self._r_domain] += [
|
||||
self.r_data.eq(fifo.r_data),
|
||||
self.r_rdy.eq(fifo.r_rdy),
|
||||
self.r_rst.eq(fifo.r_rst),
|
||||
]
|
||||
m.d.comb += [
|
||||
fifo.r_en.eq(1)
|
||||
]
|
||||
|
||||
return m
|
||||
import warnings
|
||||
warnings.warn("instead of nmigen.lib.fifo, use amaranth.lib.fifo",
|
||||
DeprecationWarning, stacklevel=2)
|
||||
|
|
|
|||
119
nmigen/lib/io.py
119
nmigen/lib/io.py
|
|
@ -1,116 +1,7 @@
|
|||
from .. import *
|
||||
from ..hdl.rec import *
|
||||
from amaranth.lib.io import *
|
||||
from amaranth.lib.io import __all__
|
||||
|
||||
|
||||
__all__ = ["pin_layout", "Pin"]
|
||||
|
||||
|
||||
def pin_layout(width, dir, xdr=0):
|
||||
"""
|
||||
Layout of the platform interface of a pin or several pins, which may be used inside
|
||||
user-defined records.
|
||||
|
||||
See :class:`Pin` for details.
|
||||
"""
|
||||
if not isinstance(width, int) or width < 1:
|
||||
raise TypeError("Width must be a positive integer, not {!r}"
|
||||
.format(width))
|
||||
if dir not in ("i", "o", "oe", "io"):
|
||||
raise TypeError("Direction must be one of \"i\", \"o\", \"io\", or \"oe\", not {!r}"""
|
||||
.format(dir))
|
||||
if not isinstance(xdr, int) or xdr < 0:
|
||||
raise TypeError("Gearing ratio must be a non-negative integer, not {!r}"
|
||||
.format(xdr))
|
||||
|
||||
fields = []
|
||||
if dir in ("i", "io"):
|
||||
if xdr > 0:
|
||||
fields.append(("i_clk", 1))
|
||||
if xdr > 2:
|
||||
fields.append(("i_fclk", 1))
|
||||
if xdr in (0, 1):
|
||||
fields.append(("i", width))
|
||||
else:
|
||||
for n in range(xdr):
|
||||
fields.append(("i{}".format(n), width))
|
||||
if dir in ("o", "oe", "io"):
|
||||
if xdr > 0:
|
||||
fields.append(("o_clk", 1))
|
||||
if xdr > 2:
|
||||
fields.append(("o_fclk", 1))
|
||||
if xdr in (0, 1):
|
||||
fields.append(("o", width))
|
||||
else:
|
||||
for n in range(xdr):
|
||||
fields.append(("o{}".format(n), width))
|
||||
if dir in ("oe", "io"):
|
||||
fields.append(("oe", 1))
|
||||
return Layout(fields)
|
||||
|
||||
|
||||
class Pin(Record):
|
||||
"""
|
||||
An interface to an I/O buffer or a group of them that provides uniform access to input, output,
|
||||
or tristate buffers that may include a 1:n gearbox. (A 1:2 gearbox is typically called "DDR".)
|
||||
|
||||
A :class:`Pin` is identical to a :class:`Record` that uses the corresponding :meth:`pin_layout`
|
||||
except that it allos accessing the parameters like ``width`` as attributes. It is legal to use
|
||||
a plain :class:`Record` anywhere a :class:`Pin` is used, provided that these attributes are
|
||||
not necessary.
|
||||
|
||||
Parameters
|
||||
----------
|
||||
width : int
|
||||
Width of the ``i``/``iN`` and ``o``/``oN`` signals.
|
||||
dir : ``"i"``, ``"o"``, ``"io"``, ``"oe"``
|
||||
Direction of the buffers. If ``"i"`` is specified, only the ``i``/``iN`` signals are
|
||||
present. If ``"o"`` is specified, only the ``o``/``oN`` signals are present. If ``"oe"`` is
|
||||
specified, the ``o``/``oN`` signals are present, and an ``oe`` signal is present.
|
||||
If ``"io"`` is specified, both the ``i``/``iN`` and ``o``/``oN`` signals are present, and
|
||||
an ``oe`` signal is present.
|
||||
xdr : int
|
||||
Gearbox ratio. If equal to 0, the I/O buffer is combinatorial, and only ``i``/``o``
|
||||
signals are present. If equal to 1, the I/O buffer is SDR, and only ``i``/``o`` signals are
|
||||
present. If greater than 1, the I/O buffer includes a gearbox, and ``iN``/``oN`` signals
|
||||
are present instead, where ``N in range(0, N)``. For example, if ``xdr=2``, the I/O buffer
|
||||
is DDR; the signal ``i0`` reflects the value at the rising edge, and the signal ``i1``
|
||||
reflects the value at the falling edge.
|
||||
name : str
|
||||
Name of the underlying record.
|
||||
|
||||
Attributes
|
||||
----------
|
||||
i_clk:
|
||||
I/O buffer input clock. Synchronizes `i*`. Present if ``xdr`` is nonzero.
|
||||
i_fclk:
|
||||
I/O buffer input fast clock. Synchronizes `i*` on higer gearbox ratios. Present if ``xdr``
|
||||
is greater than 2.
|
||||
i : Signal, out
|
||||
I/O buffer input, without gearing. Present if ``dir="i"`` or ``dir="io"``, and ``xdr`` is
|
||||
equal to 0 or 1.
|
||||
i0, i1, ... : Signal, out
|
||||
I/O buffer inputs, with gearing. Present if ``dir="i"`` or ``dir="io"``, and ``xdr`` is
|
||||
greater than 1.
|
||||
o_clk:
|
||||
I/O buffer output clock. Synchronizes `o*`, including `oe`. Present if ``xdr`` is nonzero.
|
||||
o_fclk:
|
||||
I/O buffer output fast clock. Synchronizes `o*` on higher gearbox ratios. Present if
|
||||
``xdr`` is greater than 2.
|
||||
o : Signal, in
|
||||
I/O buffer output, without gearing. Present if ``dir="o"`` or ``dir="io"``, and ``xdr`` is
|
||||
equal to 0 or 1.
|
||||
o0, o1, ... : Signal, in
|
||||
I/O buffer outputs, with gearing. Present if ``dir="o"`` or ``dir="io"``, and ``xdr`` is
|
||||
greater than 1.
|
||||
oe : Signal, in
|
||||
I/O buffer output enable. Present if ``dir="io"`` or ``dir="oe"``. Buffers generally
|
||||
cannot change direction more than once per cycle, so at most one output enable signal
|
||||
is present.
|
||||
"""
|
||||
def __init__(self, width, dir, *, xdr=0, name=None, src_loc_at=0):
|
||||
self.width = width
|
||||
self.dir = dir
|
||||
self.xdr = xdr
|
||||
|
||||
super().__init__(pin_layout(self.width, self.dir, self.xdr),
|
||||
name=name, src_loc_at=src_loc_at + 1)
|
||||
import warnings
|
||||
warnings.warn("instead of nmigen.lib.io, use amaranth.lib.io",
|
||||
DeprecationWarning, stacklevel=2)
|
||||
|
|
|
|||
|
|
@ -1,60 +1,7 @@
|
|||
from .. import *
|
||||
from amaranth.lib.scheduler import *
|
||||
from amaranth.lib.scheduler import __all__
|
||||
|
||||
|
||||
__all__ = ["RoundRobin"]
|
||||
|
||||
|
||||
class RoundRobin(Elaboratable):
|
||||
"""Round-robin scheduler.
|
||||
|
||||
For a given set of requests, the round-robin scheduler will
|
||||
grant one request. Once it grants a request, if any other
|
||||
requests are active, it grants the next active request with
|
||||
a greater number, restarting from zero once it reaches the
|
||||
highest one.
|
||||
|
||||
Use :class:`EnableInserter` to control when the scheduler
|
||||
is updated.
|
||||
|
||||
Parameters
|
||||
----------
|
||||
count : int
|
||||
Number of requests.
|
||||
|
||||
Attributes
|
||||
----------
|
||||
requests : Signal(count), in
|
||||
Set of requests.
|
||||
grant : Signal(range(count)), out
|
||||
Number of the granted request. Does not change if there are no
|
||||
active requests.
|
||||
valid : Signal(), out
|
||||
Asserted if grant corresponds to an active request. Deasserted
|
||||
otherwise, i.e. if no requests are active.
|
||||
"""
|
||||
def __init__(self, *, count):
|
||||
if not isinstance(count, int) or count < 0:
|
||||
raise ValueError("Count must be a non-negative integer, not {!r}"
|
||||
.format(count))
|
||||
self.count = count
|
||||
|
||||
self.requests = Signal(count)
|
||||
self.grant = Signal(range(count))
|
||||
self.valid = Signal()
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
|
||||
with m.Switch(self.grant):
|
||||
for i in range(self.count):
|
||||
with m.Case(i):
|
||||
for pred in reversed(range(i)):
|
||||
with m.If(self.requests[pred]):
|
||||
m.d.sync += self.grant.eq(pred)
|
||||
for succ in reversed(range(i + 1, self.count)):
|
||||
with m.If(self.requests[succ]):
|
||||
m.d.sync += self.grant.eq(succ)
|
||||
|
||||
m.d.sync += self.valid.eq(self.requests.any())
|
||||
|
||||
return m
|
||||
import warnings
|
||||
warnings.warn("instead of nmigen.lib.scheduler, use amaranth.lib.scheduler",
|
||||
DeprecationWarning, stacklevel=2)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue