Rename nMigen to Amaranth HDL.

tests/compat/support.py

@@ -1,6 +1,6 @@
-from nmigen.compat import *
-from nmigen.compat.fhdl import verilog
-from nmigen._utils import _ignore_deprecated
+from amaranth.compat import *
+from amaranth.compat.fhdl import verilog
+from amaranth._utils import _ignore_deprecated
 
 
 class SimCase:

tests/compat/test_coding.py

@@ -1,9 +1,9 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
 import unittest
 
-from nmigen.compat import *
-from nmigen.compat.genlib.coding import *
+from amaranth.compat import *
+from amaranth.compat.genlib.coding import *
 
 from .support import SimCase
 

tests/compat/test_constant.py

@@ -1,6 +1,6 @@
 import unittest
 
-from nmigen.compat import *
+from amaranth.compat import *
 
 from .support import SimCase
 

tests/compat/test_fifo.py

@@ -1,8 +1,8 @@
 import unittest
 from itertools import count
 
-from nmigen.compat import *
-from nmigen.compat.genlib.fifo import SyncFIFO
+from amaranth.compat import *
+from amaranth.compat.genlib.fifo import SyncFIFO
 
 from .support import SimCase
 

tests/compat/test_fsm.py

@@ -1,7 +1,7 @@
 import unittest
 
-from nmigen.compat import *
-from nmigen.compat.genlib.fsm import FSM
+from amaranth.compat import *
+from amaranth.compat.genlib.fsm import FSM
 
 from .support import SimCase
 

tests/compat/test_passive.py

@@ -1,6 +1,6 @@
 import unittest
 
-from nmigen.compat import *
+from amaranth.compat import *
 
 
 class PassiveCase(unittest.TestCase):

tests/compat/test_run_simulation.py

@@ -1,12 +1,12 @@
 import unittest
 
-from nmigen import Signal, Module, Elaboratable
+from amaranth import Signal, Module, Elaboratable
 
 from .support import SimCase
 
 
 class RunSimulation(SimCase, unittest.TestCase):
-    """ test for https://github.com/nmigen/nmigen/issues/344 """
+    """ test for https://github.com/amaranth-lang/amaranth/issues/344 """
 
     class TestBench(Elaboratable):
         def __init__(self):

tests/compat/test_signed.py

@@ -1,6 +1,6 @@
 import unittest
 
-from nmigen.compat import *
+from amaranth.compat import *
 
 from .support import SimCase
 

tests/compat/test_size.py

@@ -1,7 +1,7 @@
 import unittest
 
-from nmigen._utils import _ignore_deprecated
-from nmigen.compat import *
+from amaranth._utils import _ignore_deprecated
+from amaranth.compat import *
 
 
 def _same_slices(a, b):

tests/test_build_dsl.py

@@ -1,6 +1,6 @@
 from collections import OrderedDict
 
-from nmigen.build.dsl import *
+from amaranth.build.dsl import *
 
 from .utils import *
 

tests/test_build_plat.py

@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.build.plat import *
+from amaranth import *
+from amaranth.build.plat import *
 
 from .utils import *
 

tests/test_build_res.py

@@ -1,10 +1,10 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
-from nmigen import *
-from nmigen.hdl.rec import *
-from nmigen.lib.io import *
-from nmigen.build.dsl import *
-from nmigen.build.res import *
+from amaranth import *
+from amaranth.hdl.rec import *
+from amaranth.lib.io import *
+from amaranth.build.dsl import *
+from amaranth.build.res import *
 
 from .utils import *
 

tests/test_compat.py

@@ -1,5 +1,5 @@
-from nmigen.hdl.ir import Fragment
-from nmigen.compat import *
+from amaranth.hdl.ir import Fragment
+from amaranth.compat import *
 
 from .utils import *
 

tests/test_hdl_ast.py

@@ -1,7 +1,7 @@
 import warnings
 from enum import Enum
 
-from nmigen.hdl.ast import *
+from amaranth.hdl.ast import *
 
 from .utils import *
 
@@ -152,7 +152,7 @@ class ValueTestCase(FHDLTestCase):
         c = Const(0)
         self.assertIs(Value.cast(c), c)
         with self.assertRaisesRegex(TypeError,
-                r"^Object 'str' cannot be converted to an nMigen value$"):
+                r"^Object 'str' cannot be converted to an Amaranth value$"):
             Value.cast("str")
 
     def test_cast_enum(self):
@@ -170,7 +170,7 @@ class ValueTestCase(FHDLTestCase):
 
     def test_bool(self):
         with self.assertRaisesRegex(TypeError,
-                r"^Attempted to convert nMigen value to Python boolean$"):
+                r"^Attempted to convert Amaranth value to Python boolean$"):
             if Const(0):
                 pass
 

tests/test_hdl_cd.py

@@ -1,4 +1,4 @@
-from nmigen.hdl.cd import *
+from amaranth.hdl.cd import *
 
 from .utils import *
 

tests/test_hdl_dsl.py

@@ -1,11 +1,11 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
 from collections import OrderedDict
 from enum import Enum
 
-from nmigen.hdl.ast import *
-from nmigen.hdl.cd import *
-from nmigen.hdl.dsl import *
+from amaranth.hdl.ast import *
+from amaranth.hdl.cd import *
+from amaranth.hdl.dsl import *
 
 from .utils import *
 

tests/test_hdl_ir.py

@@ -1,11 +1,11 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
 from collections import OrderedDict
 
-from nmigen.hdl.ast import *
-from nmigen.hdl.cd import *
-from nmigen.hdl.ir import *
-from nmigen.hdl.mem import *
+from amaranth.hdl.ast import *
+from amaranth.hdl.cd import *
+from amaranth.hdl.ir import *
+from amaranth.hdl.mem import *
 
 from .utils import *
 

tests/test_hdl_mem.py

@@ -1,7 +1,7 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
-from nmigen.hdl.ast import *
-from nmigen.hdl.mem import *
+from amaranth.hdl.ast import *
+from amaranth.hdl.mem import *
 
 from .utils import *
 

tests/test_hdl_rec.py

@@ -1,7 +1,7 @@
 from enum import Enum
 
-from nmigen.hdl.ast import *
-from nmigen.hdl.rec import *
+from amaranth.hdl.ast import *
+from amaranth.hdl.rec import *
 
 from .utils import *
 
@@ -221,7 +221,7 @@ class RecordTestCase(FHDLTestCase):
 
         # __bool__
         with self.assertRaisesRegex(TypeError,
-                r"^Attempted to convert nMigen value to Python boolean$"):
+                r"^Attempted to convert Amaranth value to Python boolean$"):
             not r1
 
         # __invert__, __neg__

tests/test_hdl_xfrm.py

@@ -1,12 +1,12 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
 import warnings
 
-from nmigen.hdl.ast import *
-from nmigen.hdl.cd import *
-from nmigen.hdl.ir import *
-from nmigen.hdl.xfrm import *
-from nmigen.hdl.mem import *
+from amaranth.hdl.ast import *
+from amaranth.hdl.cd import *
+from amaranth.hdl.ir import *
+from amaranth.hdl.xfrm import *
+from amaranth.hdl.mem import *
 
 from .utils import *
 

tests/test_lib_cdc.py

@@ -1,8 +1,8 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
-from nmigen.hdl import *
-from nmigen.sim import *
-from nmigen.lib.cdc import *
+from amaranth.hdl import *
+from amaranth.sim import *
+from amaranth.lib.cdc import *
 
 from .utils import *
 

tests/test_lib_coding.py

@@ -1,7 +1,7 @@
-from nmigen.hdl import *
-from nmigen.asserts import *
-from nmigen.sim import *
-from nmigen.lib.coding import *
+from amaranth.hdl import *
+from amaranth.asserts import *
+from amaranth.sim import *
+from amaranth.lib.coding import *
 
 from .utils import *
 

tests/test_lib_fifo.py

@@ -1,9 +1,9 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
-from nmigen.hdl import *
-from nmigen.asserts import *
-from nmigen.sim import *
-from nmigen.lib.fifo import *
+from amaranth.hdl import *
+from amaranth.asserts import *
+from amaranth.sim import *
+from amaranth.lib.fifo import *
 
 from .utils import *
 

tests/test_lib_io.py

@@ -1,7 +1,7 @@
-from nmigen.hdl import *
-from nmigen.hdl.rec import *
-from nmigen.sim import *
-from nmigen.lib.io import *
+from amaranth.hdl import *
+from amaranth.hdl.rec import *
+from amaranth.sim import *
+from amaranth.lib.io import *
 
 from .utils import *
 

tests/test_lib_scheduler.py

@@ -1,11 +1,11 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
 import unittest
 
-from nmigen.hdl import *
-from nmigen.asserts import *
-from nmigen.sim import *
-from nmigen.lib.scheduler import *
+from amaranth.hdl import *
+from amaranth.asserts import *
+from amaranth.sim import *
+from amaranth.lib.scheduler import *
 
 from .utils import *
 

tests/test_sim.py

@@ -1,14 +1,14 @@
 import os
 from contextlib import contextmanager
 
-from nmigen._utils import flatten
-from nmigen.hdl.ast import *
-from nmigen.hdl.cd import  *
-from nmigen.hdl.mem import *
-from nmigen.hdl.rec import *
-from nmigen.hdl.dsl import  *
-from nmigen.hdl.ir import *
-from nmigen.sim import *
+from amaranth._utils import flatten
+from amaranth.hdl.ast import *
+from amaranth.hdl.cd import  *
+from amaranth.hdl.mem import *
+from amaranth.hdl.rec import *
+from amaranth.hdl.dsl import  *
+from amaranth.hdl.ir import *
+from amaranth.sim import *
 
 from .utils import *
 

tests/test_toolchain_cxx.py

@@ -3,7 +3,7 @@ import ctypes
 import tempfile
 import unittest
 
-from nmigen._toolchain.cxx import *
+from amaranth._toolchain.cxx import *
 
 
 class ToolchainCxxTestCase(unittest.TestCase):
@@ -51,7 +51,7 @@ class ToolchainCxxTestCase(unittest.TestCase):
         self.assertEqual(library.answer(), 42)
 
     def test_include(self):
-        self.include_dir = tempfile.TemporaryDirectory(prefix="nmigen_hxx_")
+        self.include_dir = tempfile.TemporaryDirectory(prefix="amaranth_hxx_")
         with open(os.path.join(self.include_dir.name, "answer.h"), "w") as f:
             f.write("#define ANSWER 42")
 

tests/utils.py

@@ -6,10 +6,10 @@ import textwrap
 import traceback
 import unittest
 
-from nmigen.hdl.ast import *
-from nmigen.hdl.ir import *
-from nmigen.back import rtlil
-from nmigen._toolchain import require_tool
+from amaranth.hdl.ast import *
+from amaranth.hdl.ir import *
+from amaranth.back import rtlil
+from amaranth._toolchain import require_tool
 
 
 __all__ = ["FHDLTestCase"]
@@ -46,7 +46,7 @@ class FHDLTestCase(unittest.TestCase):
 
         if mode == "hybrid":
             # A mix of BMC and k-induction, as per personal communication with Claire Wolf.
-            script = "setattr -unset init w:* a:nmigen.sample_reg %d"
+            script = "setattr -unset init w:* a:amaranth.sample_reg %d"
             mode   = "bmc"
         else:
             script = ""