Rename nMigen to Amaranth HDL.
This commit is contained in:
parent
0b28a97ca0
commit
909a3b8be7
200 changed files with 14493 additions and 14451 deletions
|
|
@ -1,6 +1,6 @@
|
|||
from nmigen.compat import *
|
||||
from nmigen.compat.fhdl import verilog
|
||||
from nmigen._utils import _ignore_deprecated
|
||||
from amaranth.compat import *
|
||||
from amaranth.compat.fhdl import verilog
|
||||
from amaranth._utils import _ignore_deprecated
|
||||
|
||||
|
||||
class SimCase:
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
# nmigen: UnusedElaboratable=no
|
||||
# amaranth: UnusedElaboratable=no
|
||||
|
||||
import unittest
|
||||
|
||||
from nmigen.compat import *
|
||||
from nmigen.compat.genlib.coding import *
|
||||
from amaranth.compat import *
|
||||
from amaranth.compat.genlib.coding import *
|
||||
|
||||
from .support import SimCase
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
import unittest
|
||||
|
||||
from nmigen.compat import *
|
||||
from amaranth.compat import *
|
||||
|
||||
from .support import SimCase
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
import unittest
|
||||
from itertools import count
|
||||
|
||||
from nmigen.compat import *
|
||||
from nmigen.compat.genlib.fifo import SyncFIFO
|
||||
from amaranth.compat import *
|
||||
from amaranth.compat.genlib.fifo import SyncFIFO
|
||||
|
||||
from .support import SimCase
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
import unittest
|
||||
|
||||
from nmigen.compat import *
|
||||
from nmigen.compat.genlib.fsm import FSM
|
||||
from amaranth.compat import *
|
||||
from amaranth.compat.genlib.fsm import FSM
|
||||
|
||||
from .support import SimCase
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
import unittest
|
||||
|
||||
from nmigen.compat import *
|
||||
from amaranth.compat import *
|
||||
|
||||
|
||||
class PassiveCase(unittest.TestCase):
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
import unittest
|
||||
|
||||
from nmigen import Signal, Module, Elaboratable
|
||||
from amaranth import Signal, Module, Elaboratable
|
||||
|
||||
from .support import SimCase
|
||||
|
||||
|
||||
class RunSimulation(SimCase, unittest.TestCase):
|
||||
""" test for https://github.com/nmigen/nmigen/issues/344 """
|
||||
""" test for https://github.com/amaranth-lang/amaranth/issues/344 """
|
||||
|
||||
class TestBench(Elaboratable):
|
||||
def __init__(self):
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
import unittest
|
||||
|
||||
from nmigen.compat import *
|
||||
from amaranth.compat import *
|
||||
|
||||
from .support import SimCase
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
import unittest
|
||||
|
||||
from nmigen._utils import _ignore_deprecated
|
||||
from nmigen.compat import *
|
||||
from amaranth._utils import _ignore_deprecated
|
||||
from amaranth.compat import *
|
||||
|
||||
|
||||
def _same_slices(a, b):
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue