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vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals.

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Fixes #88.
This commit is contained in:
whitequark 2019-09-20 16:11:01 +00:00
parent 378e924280
commit 91ef2f58e3
2 changed files with 3 additions and 3 deletions
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4
nmigen/vendor/lattice_ecp5.py vendored
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@ -121,7 +121,7 @@ class LatticeECP5Platform(TemplatedPlatform):
{%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
{% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%}
FREQUENCY PORT "{{signal.name}}" {{frequency}} HZ;
FREQUENCY NET "{{signal|hierarchy(".")}}" {{frequency}} HZ;
{% endfor %}
"""
}
@ -203,7 +203,7 @@ class LatticeECP5Platform(TemplatedPlatform):
{%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
{% endfor %}
{% for signal, frequency in platform.iter_clock_constraints() -%}
FREQUENCY PORT "{{signal.name}}" {{frequency/1000000}} MHZ;
FREQUENCY NET "{{signal|hierarchy("/")}}" {{frequency/1000000}} MHZ;
{% endfor %}
{{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
""",

2
nmigen/vendor/lattice_ice40.py vendored
View file

@ -97,7 +97,7 @@ class LatticeICE40Platform(TemplatedPlatform):
# {{autogenerated}}
{% for signal, frequency in platform.iter_clock_constraints() -%}
{# Clock in MHz #}
ctx.addClock("{{signal.name}}", {{frequency/1000000}})
ctx.addClock("{{signal|hierarchy(".")}}", {{frequency/1000000}})
{% endfor%}
""",
}