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back.pysim: Simulator({gtkw_signals→traces}=).

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This commit is contained in:
whitequark 2018-12-14 15:23:22 +00:00
parent e3f32a1faf
commit 9307a31678
3 changed files with 5 additions and 6 deletions
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2
examples/ctrl.py
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@ -24,7 +24,7 @@ print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
with pysim.Simulator(frag,
vcd_file=open("ctrl.vcd", "w"),
gtkw_file=open("ctrl.gtkw", "w"),
gtkw_signals=[ctr.ce, ctr.v, ctr.o]) as sim:
traces=[ctr.ce, ctr.v, ctr.o]) as sim:
sim.add_clock(1e-6)
def ce_proc():
yield; yield; yield