back.pysim: Simulator({gtkw_signals→traces}=).

2018-12-14 15:23:22 +00:00 · 2018-12-14 15:23:22 +00:00 · 9307a31678
commit 9307a31678
parent e3f32a1faf
3 changed files with 5 additions and 6 deletions
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@ -19,7 +19,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
        with Simulator(frag,
                vcd_file =open("test.vcd",  "w"),
                gtkw_file=open("test.gtkw", "w"),
-                gtkw_signals=[*isigs, osig]) as sim:
+                traces=[*isigs, osig]) as sim:
            def process():
                for isig, input in zip(isigs, inputs):
                    yield isig.eq(input)