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back.pysim: Simulator({gtkw_signals→traces}=).

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This commit is contained in:
whitequark 2018-12-14 15:23:22 +00:00
parent e3f32a1faf
commit 9307a31678
3 changed files with 5 additions and 6 deletions
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2
examples/ctrl.py
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@ -24,7 +24,7 @@ print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
with pysim.Simulator(frag, with pysim.Simulator(frag,
vcd_file=open("ctrl.vcd", "w"), vcd_file=open("ctrl.vcd", "w"),
gtkw_file=open("ctrl.gtkw", "w"), gtkw_file=open("ctrl.gtkw", "w"),
gtkw_signals=[ctr.ce, ctr.v, ctr.o]) as sim: traces=[ctr.ce, ctr.v, ctr.o]) as sim:
sim.add_clock(1e-6) sim.add_clock(1e-6)
def ce_proc(): def ce_proc():
yield; yield; yield yield; yield; yield

7
nmigen/back/pysim.py
View file

@ -191,7 +191,7 @@ class _StatementCompiler(StatementTransformer):
class Simulator: class Simulator:
def __init__(self, fragment, vcd_file=None, gtkw_file=None, gtkw_signals=()): def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
self._fragment = fragment self._fragment = fragment
self._domains = {} # str/domain -> ClockDomain self._domains = {} # str/domain -> ClockDomain
@ -221,9 +221,8 @@ class Simulator:
self._vcd_writer = None self._vcd_writer = None
self._vcd_signals = ValueDict() # signal -> set(vcd_signal) self._vcd_signals = ValueDict() # signal -> set(vcd_signal)
self._vcd_names = ValueDict() # signal -> str/name self._vcd_names = ValueDict() # signal -> str/name
self._gtkw_file = gtkw_file self._gtkw_file = gtkw_file
self._gtkw_signals = gtkw_signals self._traces = traces
def _check_process(self, process): def _check_process(self, process):
if inspect.isgeneratorfunction(process): if inspect.isgeneratorfunction(process):
@ -578,7 +577,7 @@ class Simulator:
add_trace(cd.rst) add_trace(cd.rst)
add_trace(cd.clk) add_trace(cd.clk)
for signal in self._gtkw_signals: for signal in self._traces:
add_trace(signal) add_trace(signal)
if self._vcd_file: if self._vcd_file:

2
nmigen/test/test_sim.py
View file

@ -19,7 +19,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
with Simulator(frag, with Simulator(frag,
vcd_file =open("test.vcd", "w"), vcd_file =open("test.vcd", "w"),
gtkw_file=open("test.gtkw", "w"), gtkw_file=open("test.gtkw", "w"),
gtkw_signals=[*isigs, osig]) as sim: traces=[*isigs, osig]) as sim:
def process(): def process():
for isig, input in zip(isigs, inputs): for isig, input in zip(isigs, inputs):
yield isig.eq(input) yield isig.eq(input)