hdl.ast,back.rtlil: implement Cover.

Fixes #194.

nmigen/back/pysim.py

@@ -320,6 +320,9 @@ class _StatementCompiler(StatementVisitor):
     def on_Assume(self, stmt):
         pass # :nocov:
 
+    def on_Cover(self, stmt):
+        raise NotImplementedError("Covers not yet implemented for Simulator backend.") # :nocov:
+
     def on_Switch(self, stmt):
         test  = self.rrhs_compiler(stmt.test)
         cases = []

nmigen/back/rtlil.py

@@ -654,27 +654,20 @@ class _StatementCompiler(xfrm.StatementVisitor):
         else:
             self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec)
 
-    def on_Assert(self, stmt):
+    def on_property(self, stmt):
         self(stmt._check.eq(stmt.test))
         self(stmt._en.eq(1))
 
         en_wire = self.rhs_compiler(stmt._en)
         check_wire = self.rhs_compiler(stmt._check)
-        self.state.rtlil.cell("$assert", ports={
+        self.state.rtlil.cell("$" + stmt._kind, ports={
             "\\A": check_wire,
             "\\EN": en_wire,
         }, src=src(stmt.src_loc))
 
-    def on_Assume(self, stmt):
-        self(stmt._check.eq(stmt.test))
-        self(stmt._en.eq(1))
-
-        en_wire = self.rhs_compiler(stmt._en)
-        check_wire = self.rhs_compiler(stmt._check)
-        self.state.rtlil.cell("$assume", ports={
-            "\\A": check_wire,
-            "\\EN": en_wire,
-        }, src=src(stmt.src_loc))
+    on_Assert = on_property
+    on_Assume = on_property
+    on_Cover  = on_property
 
     def on_Switch(self, stmt):
         self._check_rhs(stmt.test)