hdl.ast,back.rtlil: implement Cover.

Fixes #194.
2019-09-03 01:32:24 +00:00 · 2019-09-03 01:32:24 +00:00 · 943ce317af
commit 943ce317af
parent 2e20622046
7 changed files with 47 additions and 28 deletions
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@ -74,7 +74,7 @@ class DSLTestCase(FHDLTestCase):
    def test_d_asgn_wrong(self):
        m = Module()
        with self.assertRaises(SyntaxError,
-                msg="Only assignments, asserts, and assumes may be appended to d.sync"):
+                msg="Only assignments and property checks may be appended to d.sync"):
            m.d.sync += Switch(self.s1, {})

    def test_comb_wrong(self):