parent
d139f340b3
commit
9458de2079
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@ -526,8 +526,9 @@ def Mux(sel, val1, val0):
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Value, out
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Output ``Value``. If ``sel`` is asserted, the Mux returns ``val1``, else ``val0``.
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"""
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sel = Value.wrap(sel)
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if len(sel) != 1:
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sel = Value.wrap(sel).bool()
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sel = sel.bool()
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return Operator("m", [sel, val1, val0])
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@ -292,6 +292,10 @@ class OperatorTestCase(FHDLTestCase):
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v = Mux(s, Const(0, (4, False)), Const(0, (6, False)))
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self.assertEqual(repr(v), "(m (b (const 3'd4)) (const 4'd0) (const 6'd0))")
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def test_mux_bool(self):
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v = Mux(True, Const(0), Const(0))
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self.assertEqual(repr(v), "(m (const 1'd1) (const 1'd0) (const 1'd0))")
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def test_bool(self):
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v = Const(0).bool()
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self.assertEqual(repr(v), "(b (const 1'd0))")
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