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doc: update COMPAT_SUMMARY.

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whitequark 2019-01-19 01:01:32 +00:00
parent e3b5b2acc8
commit 94b23dd2c8
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doc/COMPAT_SUMMARY.md
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@ -14,6 +14,7 @@ API change legend:
- *a=→b=*: parameter *a* renamed to *b* - *a=→b=*: parameter *a* renamed to *b*
- *a=∼*: parameter *a* removed - *a=∼*: parameter *a* removed
- *.a=→.b*: attribute *a* renamed to *b* - *.a=→.b*: attribute *a* renamed to *b*
- *.a=∼*: attribute *a* removed
- *?*: no decision made yet - *?*: no decision made yet
When describing renames or replacements, `mod` refers to a 3rd-party package `mod` (no nMigen implementation provided), `.mod.item` refers to `nmigen.mod.item`, and "(import `.item`)" means that, while `item` is provided under `nmigen.mod.item`, it is aliased to, and should be imported from a shorter path for readability. When describing renames or replacements, `mod` refers to a 3rd-party package `mod` (no nMigen implementation provided), `.mod.item` refers to `nmigen.mod.item`, and "(import `.item`)" means that, while `item` is provided under `nmigen.mod.item`, it is aliased to, and should be imported from a shorter path for readability.
@ -49,18 +50,18 @@ Compatibility summary
- (−) `FullMemoryWE` ? - (−) `FullMemoryWE` ?
- (−) `MemoryToArray` ? - (−) `MemoryToArray` ?
- (−) `SplitMemory` ? - (−) `SplitMemory` ?
- (−) `specials` **obs** - (⊕) `specials` **obs**
- (−) `Special` ? - (⊙) `Special` **brk**
- (−) `Tristate` ? - (⊕) `Tristate` → `.lib.io.Tristate`, `target=`→`io=`
- (+) `TSTriple` → `.lib.io.TSTriple`, `bits_sign=`→`shape=` - (⊕) `TSTriple` → `.lib.io.TSTriple`, `bits_sign=`→`shape=`
- (−) `Instance` ? - (⊕) `Instance` → `.hdl.ir.Instance`
- (+) `Memory` id - (⊕) `Memory` id
- (+) `.get_port` **obs** → `.read_port()` + `.write_port()` - (⊕) `.get_port` **obs** → `.read_port()` + `.write_port()`
- (+) `_MemoryPort` **obs** - (⊕) `_MemoryPort` **obs**
<br>Note: nMigen separates read and write ports. <br>Note: nMigen separates read and write ports.
- (+) `READ_FIRST`/`WRITE_FIRST` **obs** - (⊕) `READ_FIRST`/`WRITE_FIRST` **obs**
<br>Note: `READ_FIRST` corresponds to `mem.read_port(transparent=False)`, and `WRITE_FIRST` to `mem.read_port(transparent=True)`. <br>Note: `READ_FIRST` corresponds to `mem.read_port(transparent=False)`, and `WRITE_FIRST` to `mem.read_port(transparent=True)`.
- (-) `NO_CHANGE` **brk** - (⊙) `NO_CHANGE` **brk**
<br>Note: in designs using `NO_CHANGE`, repalce it with an asynchronous read port and logic implementing required semantics explicitly. <br>Note: in designs using `NO_CHANGE`, repalce it with an asynchronous read port and logic implementing required semantics explicitly.
- (−) `structure` → `.hdl.ast` - (−) `structure` → `.hdl.ast`
- (+) `DUID` id - (+) `DUID` id
@ -79,7 +80,7 @@ Compatibility summary
- (+) `ResetSignal` id, `cd=`→`domain=` - (+) `ResetSignal` id, `cd=`→`domain=`
- (+) `_Statement` → `Statement` - (+) `_Statement` → `Statement`
- (+) `_Assign` → `Assign`, `l=`→`lhs=`, `r=`→`rhs=` - (+) `_Assign` → `Assign`, `l=`→`lhs=`, `r=`→`rhs=`
- (-) `_check_statement` **obs** → `Statement.wrap` - (+) `_check_statement` **obs** → `Statement.wrap`
- (+) `If` **obs** → `.hdl.dsl.Module.If` - (+) `If` **obs** → `.hdl.dsl.Module.If`
- (+) `Case` **obs** → `.hdl.dsl.Module.Switch` - (+) `Case` **obs** → `.hdl.dsl.Module.Switch`
- (+) `_ArrayProxy` → `.hdl.ast.ArrayProxy`, `choices=`→`elems=`, `key=`→`index=` - (+) `_ArrayProxy` → `.hdl.ast.ArrayProxy`, `choices=`→`elems=`, `key=`→`index=`
@ -122,7 +123,7 @@ Compatibility summary
- (−) `genlib` → `.lib` - (−) `genlib` → `.lib`
- (−) `cdc` ? - (−) `cdc` ?
- (−) `MultiRegImpl` ? - (−) `MultiRegImpl` ?
- (+) `MultiReg` id - (⊕) `MultiReg` id
- (−) `PulseSynchronizer` ? - (−) `PulseSynchronizer` ?
- (−) `BusSynchronizer` ? - (−) `BusSynchronizer` ?
- (−) `GrayCounter` ? - (−) `GrayCounter` ?
@ -138,11 +139,11 @@ Compatibility summary
- (−) `divider` ? - (−) `divider` ?
- (−) `Divider` ? - (−) `Divider` ?
- (−) `fifo` ? - (−) `fifo` ?
- (−) `SyncFIFO` ? - (⊕) `_FIFOInterface` → `FIFOInterface`
- (−) `SyncFIFOBuffered` ? - (⊕) `SyncFIFO` id, `.fifo=`∼
- (⊕) `SyncFIFOBuffered` id, `.fifo=`∼
- (−) `AsyncFIFO` ? - (−) `AsyncFIFO` ?
- (−) `AsyncFIFOBuffered` ? - (−) `AsyncFIFOBuffered` ?
- (−) `_FIFOInterface` ?
- (+) `fsm` **obs** - (+) `fsm` **obs**
- (+) `AnonymousState` **obs** - (+) `AnonymousState` **obs**
- (+) `NextState` **obs** - (+) `NextState` **obs**