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hdl.mem: use read_port(domain="comb") for asynchronous read ports.

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This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).

Fixes #116.
This commit is contained in:
whitequark 2019-07-01 19:56:49 +00:00
parent f75a0163f9
commit 94e8f479a5
5 changed files with 20 additions and 23 deletions
Download patch file Download diff file Expand all files Collapse all files

9
nmigen/test/test_hdl_mem.py
View file

@ -45,7 +45,6 @@ class MemoryTestCase(FHDLTestCase):
rdport = mem.read_port()
self.assertEqual(rdport.memory, mem)
self.assertEqual(rdport.domain, "sync")
self.assertEqual(rdport.synchronous, True)
self.assertEqual(rdport.transparent, True)
self.assertEqual(len(rdport.addr), 2)
self.assertEqual(len(rdport.data), 8)
@ -58,17 +57,15 @@ class MemoryTestCase(FHDLTestCase):
rdport = mem.read_port(transparent=False)
self.assertEqual(rdport.memory, mem)
self.assertEqual(rdport.domain, "sync")
self.assertEqual(rdport.synchronous, True)
self.assertEqual(rdport.transparent, False)
self.assertEqual(len(rdport.en), 1)
self.assertIsInstance(rdport.en, Signal)
def test_read_port_asynchronous(self):
mem = Memory(width=8, depth=4)
rdport = mem.read_port(synchronous=False)
rdport = mem.read_port(domain="comb")
self.assertEqual(rdport.memory, mem)
self.assertEqual(rdport.domain, "sync")
self.assertEqual(rdport.synchronous, False)
self.assertEqual(rdport.domain, "comb")
self.assertEqual(rdport.transparent, True)
self.assertEqual(len(rdport.en), 1)
self.assertIsInstance(rdport.en, Const)
@ -78,7 +75,7 @@ class MemoryTestCase(FHDLTestCase):
mem = Memory(width=8, depth=4)
with self.assertRaises(ValueError,
msg="Read port cannot be simultaneously asynchronous and non-transparent"):
mem.read_port(synchronous=False, transparent=False)
mem.read_port(domain="comb", transparent=False)
def test_write_port(self):
mem = Memory(width=8, depth=4)

2
nmigen/test/test_lib_fifo.py
View file

@ -59,7 +59,7 @@ class FIFOModel(Elaboratable, FIFOInterface):
storage = Memory(self.width, self.depth)
wrport = m.submodules.wrport = storage.write_port(domain=self.wdomain)
rdport = m.submodules.rdport = storage.read_port (synchronous=False)
rdport = m.submodules.rdport = storage.read_port (domain="comb")
produce = Signal(max=self.depth)
consume = Signal(max=self.depth)

3
nmigen/test/test_sim.py
View file

@ -431,7 +431,8 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
self.m = Module()
self.memory = Memory(width=8, depth=4, init=[0xaa, 0x55])
self.m.submodules.rdport = self.rdport = \
self.memory.read_port(synchronous=rd_synchronous, transparent=rd_transparent)
self.memory.read_port(domain="sync" if rd_synchronous else "comb",
transparent=rd_transparent)
self.m.submodules.wrport = self.wrport = \
self.memory.write_port(granularity=wr_granularity)