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back.rtlil: avoid unsoundness for division by zero.

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Fixes #238.
This commit is contained in:
whitequark 2019-10-04 07:56:06 +00:00
parent de34728bf8
commit 964c67453f
1 changed files with 12 additions and 0 deletions
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12
nmigen/back/rtlil.py
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@ -505,6 +505,18 @@ class _RHSValueCompiler(_ValueCompiler):
"B_WIDTH": rhs_bits, "B_WIDTH": rhs_bits,
"Y_WIDTH": res_bits, "Y_WIDTH": res_bits,
}, src=src(value.src_loc)) }, src=src(value.src_loc))
if value.op in ("//", "%"):
# RTLIL leaves division by zero undefined, but we require it to return zero.
divmod_res = res
res = self.s.rtlil.wire(width=res_bits, src=src(value.src_loc))
self.s.rtlil.cell("$mux", ports={
"\\A": divmod_res,
"\\B": self(ast.Const(0, (res_bits, res_sign))),
"\\S": self(lhs == 0),
"\\Y": res,
}, params={
"WIDTH": res_bits
}, src=src(value.src_loc))
return res return res
def on_Operator_mux(self, value): def on_Operator_mux(self, value):