back.rtlil: reorganize value compiler into LHS/RHS.
This also implements Cat on LHS.
This commit is contained in:
whitequark
parent
ed39748889
commit
9794e732e2
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@ -195,7 +195,94 @@ def src(src_loc):
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return "{}:{}".format(file, line)
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class _ValueTransformer(xfrm.AbstractValueTransformer):
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class _ValueCompilerState:
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def __init__(self, rtlil):
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self.rtlil = rtlil
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self.wires = ast.ValueDict()
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self.driven = ast.ValueDict()
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self.ports = ast.ValueDict()
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self.sub_name = None
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def add_driven(self, signal, sync):
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self.driven[signal] = sync
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def add_port(self, signal, kind):
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assert kind in ("i", "o", "io")
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if kind == "i":
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kind = "input"
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elif kind == "o":
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kind = "output"
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elif kind == "io":
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kind = "inout"
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self.ports[signal] = (len(self.ports), kind)
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def resolve(self, signal):
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if signal in self.wires:
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return self.wires[signal]
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if signal in self.ports:
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port_id, port_kind = self.ports[signal]
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else:
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port_id = port_kind = None
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if self.sub_name:
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wire_name = "{}_{}".format(self.sub_name, signal.name)
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else:
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wire_name = signal.name
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for attr_name, attr_signal in signal.attrs.items():
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self.rtlil.attribute(attr_name, attr_signal)
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wire_curr = self.rtlil.wire(width=signal.nbits, name=wire_name,
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port_id=port_id, port_kind=port_kind,
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src=src(signal.src_loc))
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if signal in self.driven:
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wire_next = self.rtlil.wire(width=signal.nbits, name=wire_curr + "$next",
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src=src(signal.src_loc))
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else:
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wire_next = None
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self.wires[signal] = (wire_curr, wire_next)
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return wire_curr, wire_next
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def resolve_curr(self, signal):
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wire_curr, wire_next = self.resolve(signal)
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return wire_curr
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@contextmanager
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def hierarchy(self, sub_name):
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try:
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self.sub_name = sub_name
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yield
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finally:
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self.sub_name = None
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class _ValueCompiler(xfrm.AbstractValueTransformer):
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def __init__(self, state):
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self.s = state
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def on_unknown(self, value):
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if value is None:
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return None
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else:
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super().on_unknown(value)
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def on_ClockSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_ResetSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_Slice(self, value):
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if value.end == value.start + 1:
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return "{} [{}]".format(self(value.value), value.start)
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else:
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return "{} [{}:{}]".format(self(value.value), value.end - 1, value.start)
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def on_Cat(self, value):
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return "{{ {} }}".format(" ".join(reversed([self(o) for o in value.operands])))
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class _RHSValueCompiler(_ValueCompiler):
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operator_map = {
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(1, "~"): "$not",
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(1, "-"): "$neg",
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@ -220,49 +307,6 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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(3, "m"): "$mux",
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}
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def __init__(self, rtlil):
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self.rtlil = rtlil
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self.wires = ast.ValueDict()
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self.driven = ast.ValueDict()
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self.ports = ast.ValueDict()
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self.is_lhs = False
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self.sub_name = None
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def add_driven(self, signal, sync):
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self.driven[signal] = sync
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def add_port(self, signal, kind):
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assert kind in ("i", "o", "io")
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if kind == "i":
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kind = "input"
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elif kind == "o":
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kind = "output"
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elif kind == "io":
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kind = "inout"
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self.ports[signal] = (len(self.ports), kind)
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@contextmanager
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def lhs(self):
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try:
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self.is_lhs = True
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yield
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finally:
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self.is_lhs = False
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@contextmanager
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def hierarchy(self, sub_name):
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try:
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self.sub_name = sub_name
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yield
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finally:
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self.sub_name = None
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def on_unknown(self, value):
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if value is None:
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return None
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else:
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super().on_unknown(value)
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def on_Const(self, value):
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if isinstance(value.value, str):
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return "{}'{}".format(value.nbits, value.value)
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@ -270,48 +314,15 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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return "{}'{:b}".format(value.nbits, value.value)
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def on_Signal(self, value):
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if value in self.wires:
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wire_curr, wire_next = self.wires[value]
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else:
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if value in self.ports:
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port_id, port_kind = self.ports[value]
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else:
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port_id = port_kind = None
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if self.sub_name:
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wire_name = "{}_{}".format(self.sub_name, value.name)
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else:
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wire_name = value.name
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for attr_name, attr_value in value.attrs.items():
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self.rtlil.attribute(attr_name, attr_value)
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wire_curr = self.rtlil.wire(width=value.nbits, name=wire_name,
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port_id=port_id, port_kind=port_kind,
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src=src(value.src_loc))
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if value in self.driven:
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wire_next = self.rtlil.wire(width=value.nbits, name=wire_curr + "$next",
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src=src(value.src_loc))
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else:
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wire_next = None
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self.wires[value] = (wire_curr, wire_next)
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if self.is_lhs:
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if wire_next is None:
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raise ValueError("Cannot return lhs for non-driven signal {}".format(repr(value)))
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return wire_next
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else:
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return wire_curr
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def on_ClockSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_ResetSignal(self, value):
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raise NotImplementedError # :nocov:
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wire_curr, wire_next = self.s.resolve(value)
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return wire_curr
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def on_Operator_unary(self, value):
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arg, = value.operands
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arg_bits, arg_sign = arg.shape()
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res_bits, res_sign = value.shape()
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res = self.rtlil.wire(width=res_bits)
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self.rtlil.cell(self.operator_map[(1, value.op)], ports={
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res = self.s.rtlil.wire(width=res_bits)
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self.s.rtlil.cell(self.operator_map[(1, value.op)], ports={
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"\\A": self(arg),
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"\\Y": res,
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}, params={
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@ -327,8 +338,8 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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value_bits, value_sign = value.shape()
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if new_bits > value_bits:
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res = self.rtlil.wire(width=new_bits)
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self.rtlil.cell("$pos", ports={
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res = self.s.rtlil.wire(width=new_bits)
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self.s.rtlil.cell("$pos", ports={
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"\\A": self(value),
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"\\Y": res,
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}, params={
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@ -353,8 +364,8 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
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rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
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res_bits, res_sign = value.shape()
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res = self.rtlil.wire(width=res_bits)
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self.rtlil.cell(self.operator_map[(2, value.op)], ports={
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res = self.s.rtlil.wire(width=res_bits)
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self.s.rtlil.cell(self.operator_map[(2, value.op)], ports={
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"\\A": lhs_wire,
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"\\B": rhs_wire,
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"\\Y": res,
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@ -375,8 +386,8 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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lhs_bits = rhs_bits = res_bits = max(lhs_bits, rhs_bits, res_bits)
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lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
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rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
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res = self.rtlil.wire(width=res_bits)
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self.rtlil.cell("$mux", ports={
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res = self.s.rtlil.wire(width=res_bits)
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self.s.rtlil.cell("$mux", ports={
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"\\A": lhs_wire,
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"\\B": rhs_wire,
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"\\S": self(sel),
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@ -395,20 +406,11 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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assert value.op == "m"
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return self.on_Operator_mux(value)
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else:
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raise TypeError
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def on_Slice(self, value):
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if value.end == value.start + 1:
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return "{} [{}]".format(self(value.value), value.start)
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else:
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return "{} [{}:{}]".format(self(value.value), value.end - 1, value.start)
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raise TypeError # :nocov:
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def on_Part(self, value):
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raise NotImplementedError
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def on_Cat(self, value):
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return "{{ {} }}".format(" ".join(reversed([self(o) for o in value.operands])))
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def on_Repl(self, value):
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return "{{ {} }}".format(" ".join(self(value.value) for _ in range(value.count)))
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@ -416,27 +418,52 @@ class _ValueTransformer(xfrm.AbstractValueTransformer):
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raise NotImplementedError
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class _LHSValueCompiler(_ValueCompiler):
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def on_Const(self, value):
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raise TypeError # :nocov:
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def on_Operator(self, value):
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raise TypeError # :nocov:
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def on_Signal(self, value):
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wire_curr, wire_next = self.s.resolve(value)
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if wire_next is None:
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raise ValueError("Cannot return lhs for non-driven signal {}".format(repr(value)))
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return wire_next
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def on_Part(self, value):
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raise NotImplementedError
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def on_Repl(self, value):
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raise TypeError # :nocov:
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def on_ArrayProxy(self, value):
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raise NotImplementedError
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def convert_fragment(builder, fragment, name, top):
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with builder.module(name or "anonymous", attrs={"top": 1} if top else {}) as module:
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xformer = _ValueTransformer(module)
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compiler_state = _ValueCompilerState(module)
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rhs_compiler = _RHSValueCompiler(compiler_state)
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lhs_compiler = _LHSValueCompiler(compiler_state)
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# Register all signals driven in the current fragment. This must be done first, as it
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# affects further codegen; e.g. whether sig$next signals will be generated and used.
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for domain, signal in fragment.iter_drivers():
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xformer.add_driven(signal, sync=domain is not None)
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compiler_state.add_driven(signal, sync=domain is not None)
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# Transform all signals used as ports in the current fragment eagerly and outside of
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# any hierarchy, to make sure they get sensible (non-prefixed) names.
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for signal in fragment.ports:
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xformer.add_port(signal, fragment.ports[signal])
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xformer(signal)
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compiler_state.add_port(signal, fragment.ports[signal])
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rhs_compiler(signal)
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# Transform all clocks clocks and resets eagerly and outside of any hierarchy, to make
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# sure they get sensible (non-prefixed) names. This does not affect semantics.
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for domain, _ in fragment.iter_sync():
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cd = fragment.domains[domain]
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xformer(cd.clk)
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xformer(cd.rst)
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rhs_compiler(cd.clk)
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rhs_compiler(cd.rst)
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# Transform all subfragments to their respective cells. Transforming signals connected
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# to their ports into wires eagerly makes sure they get sensible (prefixed with submodule
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@ -444,9 +471,9 @@ def convert_fragment(builder, fragment, name, top):
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for subfragment, sub_name in fragment.subfragments:
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sub_name, sub_port_map = \
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convert_fragment(builder, subfragment, top=False, name=sub_name)
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with xformer.hierarchy(sub_name):
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with compiler_state.hierarchy(sub_name):
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module.cell(sub_name, name=sub_name, ports={
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p: xformer(s) for p, s in sub_port_map.items()
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p: rhs_compiler(s) for p, s in sub_port_map.items()
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})
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with module.process() as process:
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@ -455,11 +482,10 @@ def convert_fragment(builder, fragment, name, top):
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# For every signal in sync domains, assign \sig$next to the current value (\sig).
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for domain, signal in fragment.iter_drivers():
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if domain is None:
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prev_value = xformer(ast.Const(signal.reset, signal.nbits))
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prev_value = ast.Const(signal.reset, signal.nbits)
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else:
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prev_value = xformer(signal)
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with xformer.lhs():
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case.assign(xformer(signal), prev_value)
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prev_value = signal
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case.assign(lhs_compiler(signal), rhs_compiler(prev_value))
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# Convert statements into decision trees.
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def _convert_stmts(case, stmts):
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@ -468,17 +494,15 @@ def convert_fragment(builder, fragment, name, top):
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lhs_bits, lhs_sign = stmt.lhs.shape()
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rhs_bits, rhs_sign = stmt.rhs.shape()
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if lhs_bits == rhs_bits:
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rhs_sigspec = xformer(stmt.rhs)
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rhs_sigspec = rhs_compiler(stmt.rhs)
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else:
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# In RTLIL, LHS and RHS of assignment must have exactly same width.
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rhs_sigspec = xformer.match_shape(
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rhs_sigspec = rhs_compiler.match_shape(
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stmt.rhs, lhs_bits, rhs_sign)
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with xformer.lhs():
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lhs_sigspec = xformer(stmt.lhs)
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case.assign(lhs_sigspec, rhs_sigspec)
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case.assign(lhs_compiler(stmt.lhs), rhs_sigspec)
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elif isinstance(stmt, ast.Switch):
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with case.switch(xformer(stmt.test)) as switch:
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with case.switch(rhs_compiler(stmt.test)) as switch:
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for value, nested_stmts in stmt.cases.items():
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with switch.case(value) as nested_case:
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_convert_stmts(nested_case, nested_stmts)
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@ -489,12 +513,11 @@ def convert_fragment(builder, fragment, name, top):
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_convert_stmts(case, fragment.statements)
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# For every signal in the sync domain, assign \sig's initial value (which will end up
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# as the \init reg attribute) to the reset value. Note that this assigns \sig,
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# not \sig$next.
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# as the \init reg attribute) to the reset value.
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with process.sync("init") as sync:
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for domain, signal in fragment.iter_sync():
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sync.update(xformer(signal),
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xformer(ast.Const(signal.reset, signal.nbits)))
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wire_curr, wire_next = compiler_state.resolve(signal)
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sync.update(wire_curr, rhs_compiler(ast.Const(signal.reset, signal.nbits)))
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# For every signal in every domain, assign \sig to \sig$next. The sensitivity list,
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# however, differs between domains: for comb domains, it is `always`, for sync domains
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@ -506,23 +529,22 @@ def convert_fragment(builder, fragment, name, top):
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triggers.append(("always",))
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else:
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cd = fragment.domains[domain]
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triggers.append(("posedge", xformer(cd.clk)))
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triggers.append(("posedge", compiler_state.resolve_curr(cd.clk)))
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if cd.async_reset:
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triggers.append(("posedge", xformer(cd.rst)))
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triggers.append(("posedge", compiler_state.resolve_curr(cd.rst)))
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for trigger in triggers:
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with process.sync(*trigger) as sync:
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for signal in signals:
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lhs_sigspec = xformer(signal)
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with xformer.lhs():
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sync.update(lhs_sigspec, xformer(signal))
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wire_curr, wire_next = compiler_state.resolve(signal)
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sync.update(wire_curr, wire_next)
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# Finally, collect the names we've given to our ports in RTLIL, and correlate these with
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# the signals represented by these ports. If we are a submodule, this will be necessary
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# to create a cell for us in the parent module.
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port_map = OrderedDict()
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for signal in fragment.ports:
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port_map[xformer(signal)] = signal
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port_map[compiler_state.resolve_curr(signal)] = signal
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return module.name, port_map
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