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back.verilog: allow stripping the src attribute, for cleaner output.

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whitequark 2019-04-22 14:08:01 +00:00
parent c8e92c0612
commit 97af266645
1 changed files with 7 additions and 2 deletions
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9
nmigen/back/verilog.py
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@ -11,7 +11,7 @@ class YosysError(Exception):
pass pass
def convert(*args, **kwargs): def convert(*args, strip_src=False, **kwargs):
try: try:
popen = subprocess.Popen([os.getenv("YOSYS", "yosys"), "-q", "-"], popen = subprocess.Popen([os.getenv("YOSYS", "yosys"), "-q", "-"],
stdin=subprocess.PIPE, stdin=subprocess.PIPE,
@ -26,6 +26,10 @@ def convert(*args, **kwargs):
raise YosysError("Could not find Yosys in PATH. Place `yosys` in PATH or specify " raise YosysError("Could not find Yosys in PATH. Place `yosys` in PATH or specify "
"path explicitly via the YOSYS environment variable") from e "path explicitly via the YOSYS environment variable") from e
attr_map = []
if strip_src:
attr_map.append("-remove src")
il_text = rtlil.convert(*args, **kwargs) il_text = rtlil.convert(*args, **kwargs)
verilog_text, error = popen.communicate(""" verilog_text, error = popen.communicate("""
# Convert nMigen's RTLIL to readable Verilog. # Convert nMigen's RTLIL to readable Verilog.
@ -37,8 +41,9 @@ proc_arst
proc_dff proc_dff
proc_clean proc_clean
memory_collect memory_collect
attrmap {}
write_verilog -norename write_verilog -norename
""".format(il_text)) """.format(il_text, " ".join(attr_map)))
if popen.returncode: if popen.returncode:
raise YosysError(error.strip()) raise YosysError(error.strip())
else: else: