Implement RFC 36.
This feature does not exactly follow the RFC because the RFC as written is not implementable; the treatment of async resets in `tick()` triggers had to be changed. In addition, iterating a trigger was made to watch for missed events, in case the body of the `async for` awaited for too long. Co-authored-by: Wanda <wanda-phi@users.noreply.github.com>
This commit is contained in:
Catherine
parent
5e59189c2b
commit
994fa81599
10 changed files with 1222 additions and 352 deletions
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@ -35,26 +35,25 @@ class SimulatorUnitTestCase(FHDLTestCase):
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frag.add_statements("comb", stmt)
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sim = Simulator(frag)
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def process():
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async def process(ctx):
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for isig, input in zip(isigs, inputs):
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yield isig.eq(input)
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self.assertEqual((yield osig), output.value)
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ctx.set(isig, ctx.get(input))
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self.assertEqual(ctx.get(osig), output.value)
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sim.add_testbench(process)
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with sim.write_vcd("test.vcd", "test.gtkw", traces=[*isigs, osig]):
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sim.run()
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frag = Fragment()
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sim = Simulator(frag)
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def process():
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async def process(ctx):
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for isig, input in zip(isigs, inputs):
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yield isig.eq(input)
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yield Delay(0)
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ctx.set(isig, ctx.get(input))
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if isinstance(stmt, Assign):
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yield stmt
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ctx.set(stmt.lhs, ctx.get(stmt.rhs))
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else:
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yield from stmt
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yield Delay(0)
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self.assertEqual((yield osig), output.value)
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for s in stmt:
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ctx.set(s.lhs, ctx.get(s.rhs))
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self.assertEqual(ctx.get(osig), output.value)
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sim.add_testbench(process)
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with sim.write_vcd("test.vcd", "test.gtkw", traces=[*isigs, osig]):
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sim.run()
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@ -597,18 +596,18 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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self.setUp_alu()
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with self.assertSimulation(self.m) as sim:
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sim.add_clock(1e-6)
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def process():
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yield self.a.eq(5)
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yield self.b.eq(1)
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self.assertEqual((yield self.x), 4)
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yield Tick()
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self.assertEqual((yield self.o), 6)
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yield self.s.eq(1)
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yield Tick()
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self.assertEqual((yield self.o), 4)
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yield self.s.eq(2)
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yield Tick()
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self.assertEqual((yield self.o), 0)
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async def process(ctx):
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ctx.set(self.a, 5)
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ctx.set(self.b, 1)
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self.assertEqual(ctx.get(self.x), 4)
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await ctx.tick()
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self.assertEqual(ctx.get(self.o), 6)
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ctx.set(self.s, 1)
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await ctx.tick()
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self.assertEqual(ctx.get(self.o), 4)
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ctx.set(self.s, 2)
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await ctx.tick()
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self.assertEqual(ctx.get(self.o), 0)
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sim.add_testbench(process)
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def setUp_clock_phase(self):
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@ -636,7 +635,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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sim.add_clock(period, phase=2*period/4, domain="phase180")
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sim.add_clock(period, phase=3*period/4, domain="phase270")
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def proc():
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async def proc(ctx):
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clocks = [
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self.phase0.clk,
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self.phase90.clk,
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@ -644,9 +643,9 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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self.phase270.clk
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]
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for i in range(16):
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yield Tick("check")
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await ctx.tick("check")
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for j, c in enumerate(clocks):
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self.assertEqual((yield c), self.expected[j][i])
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self.assertEqual(ctx.get(c), self.expected[j][i])
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sim.add_process(proc)
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@ -663,16 +662,15 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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sim.add_clock(1e-6, domain="sys")
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sim.add_clock(0.3e-6, domain="pix")
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def sys_process():
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yield Passive()
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yield Tick("sys")
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yield Tick("sys")
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async def sys_process(ctx):
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await ctx.tick("sys")
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await ctx.tick("sys")
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self.fail()
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def pix_process():
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yield Tick("pix")
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yield Tick("pix")
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yield Tick("pix")
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sim.add_testbench(sys_process)
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async def pix_process(ctx):
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await ctx.tick("pix")
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await ctx.tick("pix")
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await ctx.tick("pix")
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sim.add_testbench(sys_process, background=True)
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sim.add_testbench(pix_process)
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def setUp_lhs_rhs(self):
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@ -698,9 +696,9 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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m.d.sync += s.eq(0)
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with self.assertSimulation(m, deadline=100e-6) as sim:
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sim.add_clock(1e-6)
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def process():
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async def process(ctx):
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for _ in range(101):
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yield Delay(1e-6)
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await ctx.delay(1e-6)
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self.fail()
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sim.add_testbench(process)
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@ -710,12 +708,12 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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m.d.sync += s.eq(0)
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with self.assertRaises(AssertionError):
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with self.assertSimulation(m, deadline=100e-6) as sim:
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sim.add_clock(1e-6)
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def process():
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for _ in range(99):
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yield Delay(1e-6)
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self.fail()
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sim.add_testbench(process)
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sim.add_clock(1e-6)
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async def process(ctx):
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for _ in range(99):
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await ctx.delay(1e-6)
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self.fail()
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sim.add_testbench(process)
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def test_add_process_wrong(self):
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with self.assertSimulation(Module()) as sim:
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@ -818,13 +816,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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def test_memory_init(self):
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self.setUp_memory()
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with self.assertSimulation(self.m) as sim:
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def process():
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yield self.rdport.addr.eq(1)
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yield Tick()
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self.assertEqual((yield self.rdport.data), 0x55)
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yield self.rdport.addr.eq(2)
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yield Tick()
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self.assertEqual((yield self.rdport.data), 0x00)
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async def process(ctx):
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ctx.set(self.rdport.addr, 1)
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await ctx.tick()
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self.assertEqual(ctx.get(self.rdport.data), 0x55)
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ctx.set(self.rdport.addr, 2)
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await ctx.tick()
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self.assertEqual(ctx.get(self.rdport.data), 0x00)
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sim.add_clock(1e-6)
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sim.add_testbench(process)
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@ -1443,3 +1441,497 @@ class SimulatorRegressionTestCase(FHDLTestCase):
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yield c.eq(0)
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sim.add_testbench(testbench)
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sim.run()
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def test_sample(self):
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m = Module()
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m.domains.sync = cd_sync = ClockDomain()
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a = Signal(4)
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b = Signal(4)
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sim = Simulator(m)
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async def bench_a(ctx):
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_, _, av, bv = await ctx.tick().sample(a, b)
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ctx.set(a, 5)
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self.assertEqual(av, 1)
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self.assertEqual(bv, 2)
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async def bench_b(ctx):
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_, _, av, bv = await ctx.tick().sample(a, b)
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ctx.set(b, 6)
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self.assertEqual(av, 1)
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self.assertEqual(bv, 2)
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async def bench_c(ctx):
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ctx.set(a, 1)
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ctx.set(b, 2)
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ctx.set(cd_sync.clk, 1)
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ctx.set(a, 3)
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ctx.set(b, 4)
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sim.add_testbench(bench_a)
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sim.add_testbench(bench_b)
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sim.add_testbench(bench_c)
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sim.run()
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def test_latch(self):
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q = Signal(4)
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d = Signal(4)
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g = Signal()
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async def latch(ctx):
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async for dv, gv in ctx.changed(d, g):
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if gv:
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ctx.set(q, dv)
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async def testbench(ctx):
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ctx.set(d, 1)
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self.assertEqual(ctx.get(q), 0)
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ctx.set(g, 1)
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self.assertEqual(ctx.get(q), 1)
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ctx.set(d, 2)
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self.assertEqual(ctx.get(q), 2)
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ctx.set(g, 0)
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self.assertEqual(ctx.get(q), 2)
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ctx.set(d, 3)
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self.assertEqual(ctx.get(q), 2)
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sim = Simulator(Module())
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sim.add_process(latch)
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sim.add_testbench(testbench)
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sim.run()
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def test_edge(self):
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a = Signal(4)
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b = Signal(4)
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log = []
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async def monitor(ctx):
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async for res in ctx.posedge(a[0]).negedge(a[1]).sample(b):
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log.append(res)
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async def testbench(ctx):
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ctx.set(b, 8)
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ctx.set(a, 0)
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ctx.set(b, 9)
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ctx.set(a, 1)
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ctx.set(b, 10)
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ctx.set(a, 2)
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ctx.set(b, 11)
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ctx.set(a, 3)
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ctx.set(b, 12)
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ctx.set(a, 4)
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ctx.set(b, 13)
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ctx.set(a, 6)
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ctx.set(b, 14)
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ctx.set(a, 5)
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sim = Simulator(Module())
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sim.add_process(monitor)
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sim.add_testbench(testbench)
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sim.run()
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self.assertEqual(log, [
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(True, False, 9),
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(True, False, 11),
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(False, True, 12),
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(True, True, 14)
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])
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def test_delay(self):
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log = []
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async def monitor(ctx):
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async for res in ctx.delay(1).delay(2).delay(1):
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log.append(res)
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async def testbench(ctx):
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await ctx.delay(4)
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sim = Simulator(Module())
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sim.add_process(monitor)
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sim.add_testbench(testbench)
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sim.run()
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self.assertEqual(log, [
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(True, False, True),
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(True, False, True),
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(True, False, True),
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(True, False, True),
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])
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def test_timeout(self):
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a = Signal()
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log = []
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async def monitor(ctx):
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async for res in ctx.posedge(a).delay(1.5):
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log.append(res)
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async def testbench(ctx):
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await ctx.delay(0.5)
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ctx.set(a, 1)
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await ctx.delay(0.5)
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ctx.set(a, 0)
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await ctx.delay(0.5)
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ctx.set(a, 1)
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await ctx.delay(1)
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ctx.set(a, 0)
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await ctx.delay(1)
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ctx.set(a, 1)
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sim = Simulator(Module())
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sim.add_process(monitor)
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sim.add_testbench(testbench)
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sim.run()
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self.assertEqual(log, [
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(True, False),
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(True, False),
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(False, True),
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(True, False),
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])
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def test_struct(self):
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class MyStruct(data.Struct):
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x: unsigned(4)
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y: signed(4)
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a = Signal(MyStruct)
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b = Signal(MyStruct)
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m = Module()
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m.domains.sync = ClockDomain()
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log = []
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async def adder(ctx):
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async for av, in ctx.changed(a):
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ctx.set(b, {
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"x": av.y,
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"y": av.x
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})
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async def monitor(ctx):
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async for _, _, bv in ctx.tick().sample(b):
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log.append(bv)
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async def testbench(ctx):
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ctx.set(a.x, 1)
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ctx.set(a.y, 2)
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self.assertEqual(ctx.get(b.x), 2)
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self.assertEqual(ctx.get(b.y), 1)
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self.assertEqual(ctx.get(b), MyStruct.const({"x": 2, "y": 1}))
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await ctx.tick()
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ctx.set(a, MyStruct.const({"x": 3, "y": 4}))
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await ctx.tick()
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sim = Simulator(m)
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sim.add_process(adder)
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sim.add_process(monitor)
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sim.add_testbench(testbench)
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sim.add_clock(1e-6)
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sim.run()
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self.assertEqual(log, [
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MyStruct.const({"x": 2, "y": 1}),
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MyStruct.const({"x": 4, "y": 3}),
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])
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def test_valuecastable(self):
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a = Signal(4)
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b = Signal(4)
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t = Signal()
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idx = Signal()
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arr = Array([a, b])
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async def process(ctx):
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async for _ in ctx.posedge(t):
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ctx.set(arr[idx], 1)
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async def testbench(ctx):
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self.assertEqual(ctx.get(arr[idx]), 0)
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ctx.set(t, 1)
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self.assertEqual(ctx.get(a), 1)
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ctx.set(idx, 1)
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ctx.set(arr[idx], 2)
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self.assertEqual(ctx.get(b), 2)
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sim = Simulator(Module())
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sim.add_process(process)
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sim.add_testbench(testbench)
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sim.run()
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def test_tick_repeat_until(self):
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ctr = Signal(4)
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m = Module()
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m.domains.sync = cd_sync = ClockDomain()
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m.d.sync += ctr.eq(ctr + 1)
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async def testbench(ctx):
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_, _, val, = await ctx.tick(cd_sync).sample(ctr)
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self.assertEqual(val, 0)
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self.assertEqual(ctx.get(ctr), 1)
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val, = await ctx.tick(cd_sync).sample(ctr).until(ctr == 4)
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self.assertEqual(val, 4)
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self.assertEqual(ctx.get(ctr), 5)
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val, = await ctx.tick(cd_sync).sample(ctr).repeat(3)
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self.assertEqual(val, 7)
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self.assertEqual(ctx.get(ctr), 8)
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sim = Simulator(m)
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sim.add_testbench(testbench)
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sim.add_clock(1e-6)
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sim.run()
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def test_critical(self):
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ctr = Signal(4)
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m = Module()
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m.domains.sync = cd_sync = ClockDomain()
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m.d.sync += ctr.eq(ctr + 1)
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last_ctr = 0
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async def testbench(ctx):
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await ctx.tick().repeat(7)
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async def bgbench(ctx):
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nonlocal last_ctr
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while True:
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await ctx.tick()
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with ctx.critical():
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await ctx.tick().repeat(2)
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last_ctr = ctx.get(ctr)
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sim = Simulator(m)
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sim.add_testbench(testbench)
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sim.add_testbench(bgbench, background=True)
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sim.add_clock(1e-6)
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sim.run()
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self.assertEqual(last_ctr, 9)
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def test_async_reset(self):
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ctr = Signal(4)
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m = Module()
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m.domains.sync = cd_sync = ClockDomain(async_reset=True)
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m.d.sync += ctr.eq(ctr + 1)
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log = []
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async def monitor(ctx):
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async for res in ctx.tick().sample(ctr):
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log.append(res)
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async def testbench(ctx):
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await ctx.posedge(cd_sync.clk)
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await ctx.posedge(cd_sync.clk)
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await ctx.negedge(cd_sync.clk)
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ctx.set(cd_sync.rst, True)
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await ctx.negedge(cd_sync.clk)
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ctx.set(cd_sync.rst, False)
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await ctx.posedge(cd_sync.clk)
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await ctx.posedge(cd_sync.clk)
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async def repeat_bench(ctx):
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with self.assertRaises(DomainReset):
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await ctx.tick().repeat(4)
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async def until_bench(ctx):
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with self.assertRaises(DomainReset):
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await ctx.tick().until(ctr == 3)
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sim = Simulator(m)
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sim.add_process(monitor)
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sim.add_testbench(testbench)
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sim.add_testbench(repeat_bench)
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sim.add_testbench(until_bench)
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sim.add_clock(1e-6)
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sim.run()
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self.assertEqual(log, [
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(True, False, 0),
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(True, False, 1),
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(False, True, 2),
|
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(True, True, 0),
|
||||
(True, False, 0),
|
||||
(True, False, 1),
|
||||
])
|
||||
|
||||
def test_sync_reset(self):
|
||||
ctr = Signal(4)
|
||||
m = Module()
|
||||
m.domains.sync = cd_sync = ClockDomain()
|
||||
m.d.sync += ctr.eq(ctr + 1)
|
||||
|
||||
log = []
|
||||
|
||||
async def monitor(ctx):
|
||||
async for res in ctx.tick().sample(ctr):
|
||||
log.append(res)
|
||||
|
||||
async def testbench(ctx):
|
||||
await ctx.posedge(cd_sync.clk)
|
||||
await ctx.posedge(cd_sync.clk)
|
||||
await ctx.negedge(cd_sync.clk)
|
||||
ctx.set(cd_sync.rst, True)
|
||||
await ctx.negedge(cd_sync.clk)
|
||||
ctx.set(cd_sync.rst, False)
|
||||
await ctx.posedge(cd_sync.clk)
|
||||
await ctx.posedge(cd_sync.clk)
|
||||
|
||||
sim = Simulator(m)
|
||||
sim.add_process(monitor)
|
||||
sim.add_testbench(testbench)
|
||||
sim.add_clock(1e-6)
|
||||
sim.run()
|
||||
|
||||
self.assertEqual(log, [
|
||||
(True, False, 0),
|
||||
(True, False, 1),
|
||||
(True, True, 2),
|
||||
(True, False, 0),
|
||||
(True, False, 1),
|
||||
])
|
||||
|
||||
def test_broken_multiedge(self):
|
||||
a = Signal()
|
||||
|
||||
broken_trigger_hit = False
|
||||
|
||||
async def testbench(ctx):
|
||||
await ctx.delay(1)
|
||||
ctx.set(a, 1)
|
||||
ctx.set(a, 0)
|
||||
ctx.set(a, 1)
|
||||
ctx.set(a, 0)
|
||||
await ctx.delay(1)
|
||||
|
||||
async def monitor(ctx):
|
||||
nonlocal broken_trigger_hit
|
||||
try:
|
||||
async for _ in ctx.edge(a, 1):
|
||||
pass
|
||||
except BrokenTrigger:
|
||||
broken_trigger_hit = True
|
||||
|
||||
sim = Simulator(Module())
|
||||
sim.add_testbench(testbench)
|
||||
sim.add_testbench(monitor, background=True)
|
||||
sim.run()
|
||||
|
||||
self.assertTrue(broken_trigger_hit)
|
||||
|
||||
def test_broken_other_trigger(self):
|
||||
m = Module()
|
||||
m.domains.sync = ClockDomain()
|
||||
|
||||
async def testbench(ctx):
|
||||
with self.assertRaises(BrokenTrigger):
|
||||
async for _ in ctx.tick():
|
||||
await ctx.delay(2)
|
||||
|
||||
sim = Simulator(m)
|
||||
sim.add_testbench(testbench)
|
||||
sim.add_clock(1)
|
||||
sim.run()
|
||||
|
||||
def test_abandon_delay(self):
|
||||
ctr = Signal(4)
|
||||
m = Module()
|
||||
m.domains.sync = ClockDomain()
|
||||
m.d.sync += ctr.eq(ctr + 1)
|
||||
|
||||
async def testbench(ctx):
|
||||
async for _ in ctx.delay(1).delay(1):
|
||||
break
|
||||
|
||||
await ctx.tick()
|
||||
await ctx.tick()
|
||||
self.assertEqual(ctx.get(ctr), 2)
|
||||
|
||||
sim = Simulator(m)
|
||||
sim.add_testbench(testbench)
|
||||
sim.add_clock(4)
|
||||
sim.run()
|
||||
|
||||
def test_abandon_changed(self):
|
||||
ctr = Signal(4)
|
||||
a = Signal()
|
||||
m = Module()
|
||||
m.domains.sync = ClockDomain()
|
||||
m.d.sync += ctr.eq(ctr + 1)
|
||||
|
||||
async def testbench(ctx):
|
||||
async for _ in ctx.changed(a):
|
||||
break
|
||||
|
||||
await ctx.tick()
|
||||
await ctx.tick()
|
||||
self.assertEqual(ctx.get(ctr), 2)
|
||||
|
||||
async def change(ctx):
|
||||
await ctx.delay(1)
|
||||
ctx.set(a, 1)
|
||||
await ctx.delay(1)
|
||||
ctx.set(a, 0)
|
||||
await ctx.delay(1)
|
||||
ctx.set(a, 1)
|
||||
|
||||
sim = Simulator(m)
|
||||
sim.add_testbench(testbench)
|
||||
sim.add_testbench(change)
|
||||
sim.add_clock(4)
|
||||
sim.run()
|
||||
|
||||
def test_trigger_wrong(self):
|
||||
a = Signal(4)
|
||||
m = Module()
|
||||
m.domains.sync = cd_sync = ClockDomain()
|
||||
|
||||
reached_tb = False
|
||||
reached_proc = False
|
||||
|
||||
async def process(ctx):
|
||||
nonlocal reached_proc
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^`\.get\(\)` cannot be used to sample values in simulator processes; "
|
||||
r"use `\.sample\(\)` on a trigger object instead$"):
|
||||
ctx.get(a)
|
||||
reached_proc = True
|
||||
|
||||
async def testbench(ctx):
|
||||
nonlocal reached_tb
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Change trigger can only be used with a signal, not \(~ \(sig a\)\)$"):
|
||||
await ctx.changed(~a)
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Edge trigger can only be used with a single-bit signal or "
|
||||
r"a single-bit slice of a signal, not \(sig a\)$"):
|
||||
await ctx.posedge(a)
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Edge trigger polarity must be 0 or 1, not 2$"):
|
||||
await ctx.edge(a[0], 2)
|
||||
with self.assertRaisesRegex(TypeError,
|
||||
r"^Condition must be a value-like object, not 'meow'$"):
|
||||
await ctx.tick().until("meow")
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Repeat count must be a positive integer, not 0$"):
|
||||
await ctx.tick().repeat(0)
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Combinational domain does not have a clock$"):
|
||||
await ctx.tick("comb")
|
||||
with self.assertRaisesRegex(ValueError,
|
||||
r"^Context cannot be provided if a clock domain is specified directly$"):
|
||||
await ctx.tick(cd_sync, context=m)
|
||||
reached_tb = True
|
||||
|
||||
sim = Simulator(m)
|
||||
sim.add_process(process)
|
||||
sim.add_testbench(testbench)
|
||||
sim.run()
|
||||
|
||||
self.assertTrue(reached_tb)
|
||||
self.assertTrue(reached_proc)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue