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Add support for using non-compat Elaboratable instances with compat.fhdl.verilog.convert and compat.run_simulation

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Fixes #344
This commit is contained in:
Jacob Lifshay 2020-04-01 19:38:14 -07:00 • committed by whitequark
parent 6e1145e2e7
commit 995f3a147b
3 changed files with 36 additions and 2 deletions
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6
nmigen/compat/fhdl/verilog.py
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@ -4,6 +4,7 @@ from ...hdl.ir import Fragment
from ...hdl.cd import ClockDomain
from ...back import verilog
from .conv_output import ConvOutput
from .module import Module
def convert(fi, ios=None, name="top", special_overrides=dict(),
@ -17,11 +18,14 @@ def convert(fi, ios=None, name="top", special_overrides=dict(),
DeprecationWarning, stacklevel=1)
# TODO: attr_translate
if isinstance(fi, Module):
fi = fi.get_fragment()
def missing_domain(name):
if create_clock_domains:
return ClockDomain(name)
v_output = verilog.convert(
elaboratable=fi.get_fragment(),
elaboratable=fi,
name=name,
ports=ios or (),
missing_domain=missing_domain