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hdl.dsl: reword m.If(~True) warning to be more clear.

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Before this commit, it only suggested one thing (silencing it) and
that's wrong almost all of the time, so suggest the right thing
instead.
This commit is contained in:
whitequark 2019-08-03 18:52:24 +00:00
parent 8854ca03ae
commit 99d205494a
2 changed files with 7 additions and 4 deletions
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5
nmigen/hdl/dsl.py
View file

@ -171,8 +171,9 @@ class Module(_ModuleBuilderRoot, Elaboratable):
if sign:
warnings.warn("Signed values in If/Elif conditions usually result from inverting "
"Python booleans with ~, which leads to unexpected results: ~True is "
"-2, which is truthful. "
"(Silence this warning with `m.If(x)` → `m.If(x.bool())`.)",
"-2, which is truthful. Replace `~flag` with `not flag`. (If this is "
"a false positive, silence this warning with "
"`m.If(x)` → `m.If(x.bool())`.)",
SyntaxWarning, stacklevel=4)
return cond

6
nmigen/test/test_hdl_dsl.py
View file

@ -273,7 +273,8 @@ class DSLTestCase(FHDLTestCase):
with self.assertWarns(SyntaxWarning,
msg="Signed values in If/Elif conditions usually result from inverting Python "
"booleans with ~, which leads to unexpected results: ~True is -2, which is "
"truthful. (Silence this warning with `m.If(x)` → `m.If(x.bool())`.)"):
"truthful. Replace `~flag` with `not flag`. (If this is a false positive, "
"silence this warning with `m.If(x)` → `m.If(x.bool())`.)"):
with m.If(~True):
pass
@ -284,7 +285,8 @@ class DSLTestCase(FHDLTestCase):
with self.assertWarns(SyntaxWarning,
msg="Signed values in If/Elif conditions usually result from inverting Python "
"booleans with ~, which leads to unexpected results: ~True is -2, which is "
"truthful. (Silence this warning with `m.If(x)` → `m.If(x.bool())`.)"):
"truthful. Replace `~flag` with `not flag`. (If this is a false positive, "
"silence this warning with `m.If(x)` → `m.If(x.bool())`.)"):
with m.Elif(~True):
pass