lib.fifo.AsyncFIFOBuffered: fix output register accounting

nmigen/lib/fifo.py

@@ -509,7 +509,7 @@ class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
         ]
 
         r_consume_buffered = Signal()
-        m.d.comb += r_consume_buffered.eq(self.r_rdy - self.r_en)
+        m.d.comb += r_consume_buffered.eq((self.r_rdy - self.r_en) & self.r_rdy)
         m.d[self._r_domain] += self.r_level.eq(fifo.r_level + r_consume_buffered)
 
         w_consume_buffered = Signal()

tests/test_lib_fifo.py

@@ -305,7 +305,7 @@ class AsyncFIFOSimCase(FHDLTestCase):
         simulator.add_sync_process(testbench)
         simulator.run()
 
-    def check_async_fifo_level(self, fifo, fill_in, expected_level):
+    def check_async_fifo_level(self, fifo, fill_in, expected_level, read=False):
         write_done = Signal()
 
         def write_process():
@@ -320,6 +320,8 @@ class AsyncFIFOSimCase(FHDLTestCase):
             yield write_done.eq(1)
 
         def read_process():
+            if read:
+                yield fifo.r_en.eq(1)
             while not (yield write_done):
                 yield Tick("read")
             self.assertEqual((yield fifo.r_level), expected_level)
@@ -351,3 +353,7 @@ class AsyncFIFOSimCase(FHDLTestCase):
     def test_async_buffered_fifo_level_full(self):
         fifo = AsyncFIFOBuffered(width=32, depth=9, r_domain="read", w_domain="write")
         self.check_async_fifo_level(fifo, fill_in=10, expected_level=9)
+
+    def test_async_buffered_fifo_level_empty(self):
+        fifo = AsyncFIFOBuffered(width=32, depth=9, r_domain="read", w_domain="write")
+        self.check_async_fifo_level(fifo, fill_in=0, expected_level=0, read=True)