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lib.fifo.AsyncFIFOBuffered: fix output register accounting

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Robin Ole Heinemann 2021-01-03 00:17:48 +01:00 • committed by whitequark
parent 2a7a3aef87
commit 9af8201727
2 changed files with 8 additions and 2 deletions
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8
tests/test_lib_fifo.py
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@ -305,7 +305,7 @@ class AsyncFIFOSimCase(FHDLTestCase):
simulator.add_sync_process(testbench)
simulator.run()
def check_async_fifo_level(self, fifo, fill_in, expected_level):
def check_async_fifo_level(self, fifo, fill_in, expected_level, read=False):
write_done = Signal()
def write_process():
@ -320,6 +320,8 @@ class AsyncFIFOSimCase(FHDLTestCase):
yield write_done.eq(1)
def read_process():
if read:
yield fifo.r_en.eq(1)
while not (yield write_done):
yield Tick("read")
self.assertEqual((yield fifo.r_level), expected_level)
@ -351,3 +353,7 @@ class AsyncFIFOSimCase(FHDLTestCase):
def test_async_buffered_fifo_level_full(self):
fifo = AsyncFIFOBuffered(width=32, depth=9, r_domain="read", w_domain="write")
self.check_async_fifo_level(fifo, fill_in=10, expected_level=9)
def test_async_buffered_fifo_level_empty(self):
fifo = AsyncFIFOBuffered(width=32, depth=9, r_domain="read", w_domain="write")
self.check_async_fifo_level(fifo, fill_in=0, expected_level=0, read=True)