usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity

build.{res,plat}: use xdr=0 as default, not xdr=1.

Browse source 
The previous behavior was semantically incorrect.
This commit is contained in:
whitequark 2019-06-03 03:32:30 +00:00
parent cd6488c782
commit 9ba2efd86b
4 changed files with 14 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
nmigen/build/plat.py
View file

@ -169,7 +169,7 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
def get_input(self, pin, port, extras):
self._check_feature("single-ended input", pin, extras,
valid_xdrs=(1,), valid_extras=None)
valid_xdrs=(0,), valid_extras=None)
m = Module()
m.d.comb += pin.i.eq(port)
@ -177,7 +177,7 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
def get_output(self, pin, port, extras):
self._check_feature("single-ended output", pin, extras,
valid_xdrs=(1,), valid_extras=None)
valid_xdrs=(0,), valid_extras=None)
m = Module()
m.d.comb += port.eq(pin.o)
@ -185,7 +185,7 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
def get_tristate(self, pin, port, extras):
self._check_feature("single-ended tristate", pin, extras,
valid_xdrs=(1,), valid_extras=None)
valid_xdrs=(0,), valid_extras=None)
m = Module()
m.submodules += Instance("$tribuf",

6
nmigen/build/res.py
View file

@ -83,7 +83,7 @@ class ConstraintManager:
if dir is None:
dir = subsignal.io[0].dir
if xdr is None:
xdr = 1
xdr = 0
if dir not in ("i", "o", "io", "-"):
raise TypeError("Direction must be one of \"i\", \"o\", \"io\", or \"-\", "
"not {!r}"
@ -93,8 +93,8 @@ class ConstraintManager:
"direction can be changed from \"io\" to \"i\", from \"io\""
"to \"o\", or from anything to \"-\""
.format(subsignal.io[0], subsignal.io[0].dir, dir))
if not isinstance(xdr, int) or xdr < 1:
raise ValueError("Data rate of {!r} must be a positive integer, not {!r}"
if not isinstance(xdr, int) or xdr < 0:
raise ValueError("Data rate of {!r} must be a non-negative integer, not {!r}"
.format(subsignal.io[0], xdr))
return dir, xdr

4
nmigen/test/test_build_res.py
View file

@ -215,8 +215,8 @@ class ConstraintManagerTestCase(FHDLTestCase):
def test_wrong_request_with_wrong_xdr(self):
with self.assertRaises(ValueError,
msg="Data rate of (pins o A0) must be a positive integer, not 0"):
user_led = self.cm.request("user_led", 0, xdr=0)
msg="Data rate of (pins o A0) must be a non-negative integer, not -1"):
user_led = self.cm.request("user_led", 0, xdr=-1)
def test_wrong_request_with_xdr_dict(self):
with self.assertRaises(TypeError,

6
nmigen/vendor/fpga/lattice_ice40.py vendored
View file

@ -117,6 +117,8 @@ class LatticeICE40Platform(TemplatedPlatform):
return m
def get_input(self, pin, port, extras):
self._check_feature("single-ended input", pin, extras,
valid_xdrs=(0,), valid_extras=True)
return self._get_io_buffer(port, extras, lambda bit: [
# PIN_NO_OUTPUT|PIN_INPUT
("p", "PIN_TYPE", 0b0000_01),
@ -124,6 +126,8 @@ class LatticeICE40Platform(TemplatedPlatform):
])
def get_output(self, pin, port, extras):
self._check_feature("single-ended output", pin, extras,
valid_xdrs=(0,), valid_extras=True)
return self._get_io_buffer(port, extras, lambda bit: [
# PIN_OUTPUT|PIN_INPUT_REGISTERED
("p", "PIN_TYPE", 0b0110_00),
@ -131,6 +135,8 @@ class LatticeICE40Platform(TemplatedPlatform):
])
def get_tristate(self, pin, port, extras):
self._check_feature("single-ended tristate", pin, extras,
valid_xdrs=(0,), valid_extras=True)
return self._get_io_buffer(port, extras, lambda bit: [
# PIN_OUTPUT_TRISTATE|PIN_INPUT_REGISTERED
("p", "PIN_TYPE", 0b1010_00),