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build.{res,plat}: use xdr=0 as default, not xdr=1.

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The previous behavior was semantically incorrect.
This commit is contained in:
whitequark 2019-06-03 03:32:30 +00:00
parent cd6488c782
commit 9ba2efd86b
4 changed files with 14 additions and 8 deletions
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6
nmigen/vendor/fpga/lattice_ice40.py vendored
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@ -117,6 +117,8 @@ class LatticeICE40Platform(TemplatedPlatform):
return m
def get_input(self, pin, port, extras):
self._check_feature("single-ended input", pin, extras,
valid_xdrs=(0,), valid_extras=True)
return self._get_io_buffer(port, extras, lambda bit: [
# PIN_NO_OUTPUT|PIN_INPUT
("p", "PIN_TYPE", 0b0000_01),
@ -124,6 +126,8 @@ class LatticeICE40Platform(TemplatedPlatform):
])
def get_output(self, pin, port, extras):
self._check_feature("single-ended output", pin, extras,
valid_xdrs=(0,), valid_extras=True)
return self._get_io_buffer(port, extras, lambda bit: [
# PIN_OUTPUT|PIN_INPUT_REGISTERED
("p", "PIN_TYPE", 0b0110_00),
@ -131,6 +135,8 @@ class LatticeICE40Platform(TemplatedPlatform):
])
def get_tristate(self, pin, port, extras):
self._check_feature("single-ended tristate", pin, extras,
valid_xdrs=(0,), valid_extras=True)
return self._get_io_buffer(port, extras, lambda bit: [
# PIN_OUTPUT_TRISTATE|PIN_INPUT_REGISTERED
("p", "PIN_TYPE", 0b1010_00),