hdl.ir: don't expose as ports missing domains added via elaboratables.

The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.

nmigen/hdl/ir.py

@@ -364,6 +364,9 @@ class Fragment:
                     raise DomainError("Domain '{}' is used but not defined".format(domain_name))
                 if type(value) is ClockDomain:
                     domain = value
+                    # Only expose ports on clock domains returned directly, i.e. not as a part of
+                    # a fragment driving that domain.
+                    new_domains.append(domain)
                 else:
                     new_fragment = Fragment.get(value, platform=None)
                     if new_fragment.domains.keys() != {domain_name}:
@@ -377,7 +380,6 @@ class Fragment:
                     self.add_subfragment(new_fragment)
                     domain = new_fragment.domains[domain_name]
                 self.add_domains(domain)
-                new_domains.append(domain)
         return new_domains
 
     def _propagate_domains(self, missing_domain):

nmigen/test/test_hdl_ir.py

@@ -415,7 +415,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
         new_domains = f1._propagate_domains(missing_domain=lambda name: f2)
         self.assertEqual(f1.domains.keys(), {"sync"})
         self.assertEqual(f1.domains["sync"], f2.domains["sync"])
-        self.assertEqual(new_domains, [f1.domains["sync"]])
+        self.assertEqual(new_domains, [])
         self.assertEqual(f1.subfragments, [
             (f2, None)
         ])