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hdl.ir: don't expose as ports missing domains added via elaboratables.

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The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
This commit is contained in:
whitequark 2019-08-03 16:39:21 +00:00
parent 21f2f8c46e
commit 9c28b61d9f
2 changed files with 4 additions and 2 deletions
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4
nmigen/hdl/ir.py
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@ -364,6 +364,9 @@ class Fragment:
raise DomainError("Domain '{}' is used but not defined".format(domain_name))
if type(value) is ClockDomain:
domain = value
# Only expose ports on clock domains returned directly, i.e. not as a part of
# a fragment driving that domain.
new_domains.append(domain)
else:
new_fragment = Fragment.get(value, platform=None)
if new_fragment.domains.keys() != {domain_name}:
@ -377,7 +380,6 @@ class Fragment:
self.add_subfragment(new_fragment)
domain = new_fragment.domains[domain_name]
self.add_domains(domain)
new_domains.append(domain)
return new_domains
def _propagate_domains(self, missing_domain):