hdl.ir: don't expose as ports missing domains added via elaboratables.

The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.

nmigen/test/test_hdl_ir.py

@@ -415,7 +415,7 @@ class FragmentDomainsTestCase(FHDLTestCase):
         new_domains = f1._propagate_domains(missing_domain=lambda name: f2)
         self.assertEqual(f1.domains.keys(), {"sync"})
         self.assertEqual(f1.domains["sync"], f2.domains["sync"])
-        self.assertEqual(new_domains, [f1.domains["sync"]])
+        self.assertEqual(new_domains, [])
         self.assertEqual(f1.subfragments, [
             (f2, None)
         ])