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back.pysim: create unique ResetSynchronizer internal domains.

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Commit 300d47ca introduced the same bug commit 779f3ee9 was trying to
avoid, but now only in the simulator. Since the names in simulator
don't have to make any sense, just use DUID to generate them.
This commit is contained in:
whitequark 2019-06-28 08:34:02 +00:00
parent 300d47ca2e
commit 9c54d0c061
1 changed files with 6 additions and 4 deletions
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10
nmigen/back/pysim.py
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@ -10,6 +10,7 @@ from ..tools import flatten
from ..hdl.ast import * from ..hdl.ast import *
from ..hdl.ir import * from ..hdl.ir import *
from ..hdl.xfrm import ValueVisitor, StatementVisitor from ..hdl.xfrm import ValueVisitor, StatementVisitor
from ..hdl.ast import DUID
from ..hdl.dsl import Module from ..hdl.dsl import Module
from ..hdl.cd import ClockDomain from ..hdl.cd import ClockDomain
@ -356,12 +357,13 @@ class _StatementCompiler(StatementVisitor):
class _SimulatorPlatform: class _SimulatorPlatform:
def get_reset_sync(self, reset_sync): def get_reset_sync(self, reset_sync):
m = Module() m = Module()
m.domains += ClockDomain("_reset_sync", async_reset=True) cd = ClockDomain("_reset_sync_{}".format(DUID().duid), async_reset=True)
m.domains += cd
for i, o in zip((0, *reset_sync._regs), reset_sync._regs): for i, o in zip((0, *reset_sync._regs), reset_sync._regs):
m.d._reset_sync += o.eq(i) m.d[cd.name] += o.eq(i)
m.d.comb += [ m.d.comb += [
ClockSignal("_reset_sync").eq(ClockSignal(reset_sync.domain)), ClockSignal(cd.name).eq(ClockSignal(reset_sync.domain)),
ResetSignal("_reset_sync").eq(reset_sync.arst), ResetSignal(cd.name).eq(reset_sync.arst),
ResetSignal(reset_sync.domain).eq(reset_sync._regs[-1]) ResetSignal(reset_sync.domain).eq(reset_sync._regs[-1])
] ]
return m return m