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hdl.dsl: error on Elif immediately nested in an If.

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I.e. on this code, which is currently not only wrongly accepted but
also results in completely unexpected RTL:

    with m.If(...):
        with m.Elif(...):
            ...

Fixes #500.
This commit is contained in:
whitequark 2020-10-22 13:23:06 +00:00
parent 2c505deacc
commit 9d62cbefa5
2 changed files with 9 additions and 1 deletions
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2
nmigen/hdl/dsl.py
View file

@ -249,7 +249,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
cond = self._check_signed_cond(cond) cond = self._check_signed_cond(cond)
src_loc = tracer.get_src_loc(src_loc_at=1) src_loc = tracer.get_src_loc(src_loc_at=1)
if_data = self._get_ctrl("If") if_data = self._get_ctrl("If")
if if_data is None: if if_data is None or len(if_data["tests"]) == 0:
raise SyntaxError("Elif without preceding If") raise SyntaxError("Elif without preceding If")
try: try:
_outer_case, self._statements = self._statements, [] _outer_case, self._statements = self._statements, []

8
tests/test_hdl_dsl.py
View file

@ -266,6 +266,14 @@ class DSLTestCase(FHDLTestCase):
with m.Elif(self.s2): with m.Elif(self.s2):
pass pass
def test_Elif_wrong_nested(self):
m = Module()
with m.If(self.s1):
with self.assertRaisesRegex(SyntaxError,
r"^Elif without preceding If$"):
with m.Elif(self.s2):
pass
def test_Else_wrong(self): def test_Else_wrong(self):
m = Module() m = Module()
with self.assertRaisesRegex(SyntaxError, with self.assertRaisesRegex(SyntaxError,