Implement RFC 27: Testbench processes for the simulator.
Co-authored-by: Wanda <wanda@phinode.net>
This commit is contained in:
Catherine
parent
f48b8650c4
commit
9e75962c35
7 changed files with 279 additions and 143 deletions
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@ -26,13 +26,13 @@ class FFSynchronizerTestCase(FHDLTestCase):
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def process():
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self.assertEqual((yield o), 0)
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yield i.eq(1)
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yield Tick()
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yield
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self.assertEqual((yield o), 0)
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yield Tick()
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yield
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self.assertEqual((yield o), 0)
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yield Tick()
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yield
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self.assertEqual((yield o), 1)
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sim.add_process(process)
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sim.add_sync_process(process)
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sim.run()
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def test_reset_value(self):
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@ -45,13 +45,13 @@ class FFSynchronizerTestCase(FHDLTestCase):
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def process():
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self.assertEqual((yield o), 1)
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yield i.eq(0)
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yield Tick()
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yield
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self.assertEqual((yield o), 1)
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yield Tick()
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yield
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self.assertEqual((yield o), 1)
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yield Tick()
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yield
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self.assertEqual((yield o), 0)
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sim.add_process(process)
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sim.add_sync_process(process)
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sim.run()
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@ -90,28 +90,27 @@ class AsyncFFSynchronizerTestCase(FHDLTestCase):
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# initial reset
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self.assertEqual((yield i), 0)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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yield i.eq(1)
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yield Delay(1e-8)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield i.eq(0)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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sim.add_process(process)
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yield Tick()
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sim.add_testbench(process)
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with sim.write_vcd("test.vcd"):
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sim.run()
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@ -128,28 +127,27 @@ class AsyncFFSynchronizerTestCase(FHDLTestCase):
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# initial reset
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self.assertEqual((yield i), 1)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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yield i.eq(0)
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yield Delay(1e-8)
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield i.eq(1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield o), 0)
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yield Tick(); yield Delay(1e-8)
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sim.add_process(process)
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yield Tick()
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sim.add_testbench(process)
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with sim.write_vcd("test.vcd"):
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sim.run()
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@ -176,28 +174,28 @@ class ResetSynchronizerTestCase(FHDLTestCase):
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def process():
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# initial reset
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield s), 0)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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yield arst.eq(1)
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yield Delay(1e-8)
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self.assertEqual((yield s), 0)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield s), 1)
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yield arst.eq(0)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield s), 1)
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yield Tick(); yield Delay(1e-8)
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yield Tick()
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self.assertEqual((yield s), 0)
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yield Tick(); yield Delay(1e-8)
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sim.add_process(process)
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yield Tick()
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sim.add_testbench(process)
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with sim.write_vcd("test.vcd"):
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sim.run()
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@ -223,17 +221,17 @@ class PulseSynchronizerTestCase(FHDLTestCase):
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yield ps.i.eq(0)
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# TODO: think about reset
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for n in range(5):
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yield Tick()
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yield
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# Make sure no pulses are generated in quiescent state
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for n in range(3):
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yield Tick()
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yield
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self.assertEqual((yield ps.o), 0)
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# Check conservation of pulses
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accum = 0
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for n in range(10):
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yield ps.i.eq(1 if n < 4 else 0)
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yield Tick()
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yield
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accum += yield ps.o
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self.assertEqual(accum, 4)
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sim.add_process(process)
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sim.add_sync_process(process)
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sim.run()
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@ -14,22 +14,19 @@ class EncoderTestCase(FHDLTestCase):
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self.assertEqual((yield enc.o), 0)
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yield enc.i.eq(0b0001)
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yield Settle()
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self.assertEqual((yield enc.n), 0)
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self.assertEqual((yield enc.o), 0)
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yield enc.i.eq(0b0100)
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yield Settle()
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self.assertEqual((yield enc.n), 0)
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self.assertEqual((yield enc.o), 2)
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yield enc.i.eq(0b0110)
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yield Settle()
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self.assertEqual((yield enc.n), 1)
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self.assertEqual((yield enc.o), 0)
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sim = Simulator(enc)
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sim.add_process(process)
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sim.add_testbench(process)
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sim.run()
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@ -41,22 +38,19 @@ class PriorityEncoderTestCase(FHDLTestCase):
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self.assertEqual((yield enc.o), 0)
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yield enc.i.eq(0b0001)
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yield Settle()
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self.assertEqual((yield enc.n), 0)
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self.assertEqual((yield enc.o), 0)
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yield enc.i.eq(0b0100)
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yield Settle()
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self.assertEqual((yield enc.n), 0)
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self.assertEqual((yield enc.o), 2)
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yield enc.i.eq(0b0110)
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yield Settle()
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self.assertEqual((yield enc.n), 0)
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self.assertEqual((yield enc.o), 1)
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sim = Simulator(enc)
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sim.add_process(process)
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sim.add_testbench(process)
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sim.run()
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@ -67,19 +61,16 @@ class DecoderTestCase(FHDLTestCase):
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self.assertEqual((yield dec.o), 0b0001)
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yield dec.i.eq(1)
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yield Settle()
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self.assertEqual((yield dec.o), 0b0010)
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yield dec.i.eq(3)
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yield Settle()
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self.assertEqual((yield dec.o), 0b1000)
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yield dec.n.eq(1)
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yield Settle()
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self.assertEqual((yield dec.o), 0b0000)
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sim = Simulator(dec)
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sim.add_process(process)
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sim.add_testbench(process)
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sim.run()
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@ -870,7 +870,7 @@ class RFCExamplesTestCase(TestCase):
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def simulate(m):
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def wrapper(fn):
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sim = Simulator(m)
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sim.add_process(fn)
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sim.add_testbench(fn)
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sim.run()
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return wrapper
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@ -315,10 +315,10 @@ class AsyncFIFOSimCase(FHDLTestCase):
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for i in range(fill_in):
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yield fifo.w_data.eq(i)
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yield fifo.w_en.eq(1)
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yield Tick("write")
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yield
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yield fifo.w_en.eq(0)
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yield Tick("write")
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yield Tick("write")
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yield
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yield
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self.assertEqual((yield fifo.w_level), expected_level)
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yield write_done.eq(1)
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@ -326,7 +326,7 @@ class AsyncFIFOSimCase(FHDLTestCase):
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if read:
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yield fifo.r_en.eq(1)
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while not (yield write_done):
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yield Tick("read")
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yield
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self.assertEqual((yield fifo.r_level), expected_level)
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simulator = Simulator(fifo)
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@ -35,9 +35,8 @@ class SimulatorUnitTestCase(FHDLTestCase):
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def process():
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for isig, input in zip(isigs, inputs):
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yield isig.eq(input)
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yield Settle()
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self.assertEqual((yield osig), output.value)
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sim.add_process(process)
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sim.add_testbench(process)
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with sim.write_vcd("test.vcd", "test.gtkw", traces=[*isigs, osig]):
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sim.run()
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@ -436,28 +435,29 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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def test_counter_process(self):
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self.setUp_counter()
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with self.assertSimulation(self.m) as sim:
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def process():
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self.assertEqual((yield self.count), 4)
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yield Delay(1e-6)
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self.assertEqual((yield self.count), 4)
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yield self.sync.clk.eq(1)
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self.assertEqual((yield self.count), 4)
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yield Settle()
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self.assertEqual((yield self.count), 5)
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yield Delay(1e-6)
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self.assertEqual((yield self.count), 5)
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yield self.sync.clk.eq(0)
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self.assertEqual((yield self.count), 5)
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yield Settle()
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self.assertEqual((yield self.count), 5)
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for _ in range(3):
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with _ignore_deprecated():
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with self.assertSimulation(self.m) as sim:
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def process():
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self.assertEqual((yield self.count), 4)
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yield Delay(1e-6)
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self.assertEqual((yield self.count), 4)
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yield self.sync.clk.eq(1)
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self.assertEqual((yield self.count), 4)
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yield Settle()
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self.assertEqual((yield self.count), 5)
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yield Delay(1e-6)
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self.assertEqual((yield self.count), 5)
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yield self.sync.clk.eq(0)
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self.assertEqual((yield self.count), 0)
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sim.add_process(process)
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self.assertEqual((yield self.count), 5)
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yield Settle()
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self.assertEqual((yield self.count), 5)
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for _ in range(3):
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yield Delay(1e-6)
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yield self.sync.clk.eq(1)
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yield Delay(1e-6)
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yield self.sync.clk.eq(0)
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self.assertEqual((yield self.count), 0)
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sim.add_process(process)
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def test_counter_clock_and_sync_process(self):
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self.setUp_counter()
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@ -611,10 +611,9 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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def process():
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yield self.i.eq(0b10101010)
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yield self.i[:4].eq(-1)
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yield Settle()
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self.assertEqual((yield self.i[:4]), 0b1111)
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self.assertEqual((yield self.i), 0b10101111)
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sim.add_process(process)
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sim.add_testbench(process)
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def test_run_until(self):
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m = Module()
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@ -626,7 +625,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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for _ in range(101):
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yield Delay(1e-6)
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self.fail()
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sim.add_process(process)
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sim.add_testbench(process)
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def test_run_until_fail(self):
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m = Module()
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@ -639,13 +638,13 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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for _ in range(99):
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yield Delay(1e-6)
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self.fail()
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sim.add_process(process)
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sim.add_testbench(process)
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def test_add_process_wrong(self):
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with self.assertSimulation(Module()) as sim:
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with self.assertRaisesRegex(TypeError,
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r"^Cannot add a process 1 because it is not a generator function$"):
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sim.add_process(1)
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sim.add_sync_process(1)
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def test_add_process_wrong_generator(self):
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with self.assertSimulation(Module()) as sim:
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@ -653,7 +652,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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r"^Cannot add a process <.+?> because it is not a generator function$"):
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def process():
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yield Delay()
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sim.add_process(process())
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sim.add_sync_process(process())
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def test_add_clock_wrong_twice(self):
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m = Module()
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@ -679,14 +678,47 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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def test_command_wrong(self):
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survived = False
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with self.assertSimulation(Module()) as sim:
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with _ignore_deprecated():
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with self.assertSimulation(Module()) as sim:
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def process():
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nonlocal survived
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with self.assertRaisesRegex(TypeError,
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r"Received unsupported command 1 from process .+?"):
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yield 1
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survived = True
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sim.add_process(process)
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self.assertTrue(survived)
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def test_sync_command_deprecated(self):
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survived = False
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m = Module()
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dummy = Signal()
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m.d.sync += dummy.eq(1)
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with self.assertSimulation(m) as sim:
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def process():
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nonlocal survived
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with self.assertWarnsRegex(DeprecationWarning,
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r"Using `Delay` is deprecated within `add_sync_process`"):
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yield Delay(1e-8)
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survived = True
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sim.add_sync_process(process)
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sim.add_clock(1e-6)
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self.assertTrue(survived)
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def test_sync_command_wrong(self):
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survived = False
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m = Module()
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dummy = Signal()
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m.d.sync += dummy.eq(1)
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with self.assertSimulation(m) as sim:
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def process():
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nonlocal survived
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with self.assertRaisesRegex(TypeError,
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r"Received unsupported command 1 from process .+?"):
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yield 1
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survived = True
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sim.add_process(process)
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sim.add_sync_process(process)
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sim.add_clock(1e-6)
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self.assertTrue(survived)
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def test_value_castable(self):
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@ -701,13 +733,19 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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a = Array([1,2,3])
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a[MyValue()]
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def test_bench_command_wrong(self):
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survived = False
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with self.assertSimulation(Module()) as sim:
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def process():
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nonlocal survived
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yield MyValue()
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with self.assertWarnsRegex(DeprecationWarning,
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r"The `Settle` command is deprecated"):
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settle = Settle()
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with self.assertRaisesRegex(TypeError,
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r"Command \(settle\) is not allowed in testbenches"):
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yield settle
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survived = True
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sim.add_process(process)
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sim.add_testbench(process)
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self.assertTrue(survived)
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def setUp_memory(self, rd_synchronous=True, rd_transparent=True, wr_granularity=None):
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@ -755,23 +793,23 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
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def process():
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yield self.wrport.data.eq(0x50)
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yield self.wrport.en.eq(0b00)
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yield
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yield Tick()
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yield self.wrport.en.eq(0)
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yield
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yield Tick()
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self.assertEqual((yield self.rdport.data), 0xaa)
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yield self.wrport.en.eq(0b10)
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yield
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yield Tick()
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yield self.wrport.en.eq(0)
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yield
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yield Tick()
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self.assertEqual((yield self.rdport.data), 0x5a)
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yield self.wrport.data.eq(0x33)
|
||||
yield self.wrport.en.eq(0b01)
|
||||
yield
|
||||
yield Tick()
|
||||
yield self.wrport.en.eq(0)
|
||||
yield
|
||||
yield Tick()
|
||||
self.assertEqual((yield self.rdport.data), 0x53)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_memory_read_before_write(self):
|
||||
self.setUp_memory(rd_transparent=False)
|
||||
|
|
@ -779,52 +817,46 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
def process():
|
||||
yield self.wrport.data.eq(0x33)
|
||||
yield self.wrport.en.eq(1)
|
||||
yield
|
||||
yield Tick()
|
||||
self.assertEqual((yield self.rdport.data), 0xaa)
|
||||
yield
|
||||
self.assertEqual((yield self.rdport.data), 0xaa)
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield self.rdport.data), 0x33)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_memory_write_through(self):
|
||||
self.setUp_memory(rd_transparent=True)
|
||||
with self.assertSimulation(self.m) as sim:
|
||||
def process():
|
||||
yield Tick()
|
||||
yield self.wrport.data.eq(0x33)
|
||||
yield self.wrport.en.eq(1)
|
||||
yield
|
||||
self.assertEqual((yield self.rdport.data), 0xaa)
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield self.rdport.data), 0x33)
|
||||
yield
|
||||
yield Tick()
|
||||
yield self.rdport.addr.eq(1)
|
||||
yield Settle()
|
||||
self.assertEqual((yield self.rdport.data), 0x33)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_memory_async_read_write(self):
|
||||
self.setUp_memory(rd_synchronous=False)
|
||||
with self.assertSimulation(self.m) as sim:
|
||||
def process():
|
||||
yield self.rdport.addr.eq(0)
|
||||
yield Settle()
|
||||
self.assertEqual((yield self.rdport.data), 0xaa)
|
||||
yield self.rdport.addr.eq(1)
|
||||
yield Settle()
|
||||
self.assertEqual((yield self.rdport.data), 0x55)
|
||||
yield self.rdport.addr.eq(0)
|
||||
yield self.wrport.addr.eq(0)
|
||||
yield self.wrport.data.eq(0x33)
|
||||
yield self.wrport.en.eq(1)
|
||||
yield Tick("sync")
|
||||
self.assertEqual((yield self.rdport.data), 0xaa)
|
||||
yield Settle()
|
||||
yield Tick("sync")
|
||||
self.assertEqual((yield self.rdport.data), 0x33)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_process(process)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_memory_read_only(self):
|
||||
self.m = Module()
|
||||
|
|
@ -841,6 +873,49 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
|
||||
def test_comb_bench_process(self):
|
||||
m = Module()
|
||||
a = Signal(reset=1)
|
||||
b = Signal()
|
||||
m.d.comb += b.eq(a)
|
||||
with self.assertSimulation(m) as sim:
|
||||
def process():
|
||||
self.assertEqual((yield a), 1)
|
||||
self.assertEqual((yield b), 1)
|
||||
yield a.eq(0)
|
||||
self.assertEqual((yield a), 0)
|
||||
self.assertEqual((yield b), 0)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_sync_bench_process(self):
|
||||
m = Module()
|
||||
a = Signal(reset=1)
|
||||
b = Signal()
|
||||
m.d.sync += b.eq(a)
|
||||
t = Signal()
|
||||
m.d.sync += t.eq(~t)
|
||||
with self.assertSimulation(m) as sim:
|
||||
def process():
|
||||
self.assertEqual((yield a), 1)
|
||||
self.assertEqual((yield b), 0)
|
||||
self.assertEqual((yield t), 0)
|
||||
yield Tick()
|
||||
self.assertEqual((yield a), 1)
|
||||
self.assertEqual((yield b), 1)
|
||||
self.assertEqual((yield t), 1)
|
||||
yield Tick()
|
||||
self.assertEqual((yield a), 1)
|
||||
self.assertEqual((yield b), 1)
|
||||
self.assertEqual((yield t), 0)
|
||||
yield a.eq(0)
|
||||
self.assertEqual((yield a), 0)
|
||||
self.assertEqual((yield b), 1)
|
||||
yield Tick()
|
||||
self.assertEqual((yield a), 0)
|
||||
self.assertEqual((yield b), 0)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_memory_transparency_simple(self):
|
||||
m = Module()
|
||||
init = [0x11, 0x22, 0x33, 0x44]
|
||||
|
|
@ -850,41 +925,35 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
with self.assertSimulation(m) as sim:
|
||||
def process():
|
||||
yield rdport.addr.eq(0)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x11)
|
||||
yield rdport.addr.eq(1)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x22)
|
||||
yield wrport.addr.eq(0)
|
||||
yield wrport.data.eq(0x44444444)
|
||||
yield wrport.en.eq(1)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x22)
|
||||
yield wrport.addr.eq(1)
|
||||
yield wrport.data.eq(0x55)
|
||||
yield wrport.en.eq(1)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x55)
|
||||
yield wrport.addr.eq(1)
|
||||
yield wrport.data.eq(0x66)
|
||||
yield wrport.en.eq(1)
|
||||
yield rdport.en.eq(0)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x55)
|
||||
yield wrport.addr.eq(2)
|
||||
yield wrport.data.eq(0x77)
|
||||
yield wrport.en.eq(1)
|
||||
yield rdport.en.eq(1)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x66)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_memory_transparency_multibit(self):
|
||||
m = Module()
|
||||
|
|
@ -895,41 +964,35 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
|
|||
with self.assertSimulation(m) as sim:
|
||||
def process():
|
||||
yield rdport.addr.eq(0)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x11111111)
|
||||
yield rdport.addr.eq(1)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x22222222)
|
||||
yield wrport.addr.eq(0)
|
||||
yield wrport.data.eq(0x44444444)
|
||||
yield wrport.en.eq(1)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x22222222)
|
||||
yield wrport.addr.eq(1)
|
||||
yield wrport.data.eq(0x55555555)
|
||||
yield wrport.en.eq(1)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x22222255)
|
||||
yield wrport.addr.eq(1)
|
||||
yield wrport.data.eq(0x66666666)
|
||||
yield wrport.en.eq(2)
|
||||
yield rdport.en.eq(0)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x22222255)
|
||||
yield wrport.addr.eq(1)
|
||||
yield wrport.data.eq(0x77777777)
|
||||
yield wrport.en.eq(4)
|
||||
yield rdport.en.eq(1)
|
||||
yield
|
||||
yield Settle()
|
||||
yield Tick()
|
||||
self.assertEqual((yield rdport.data), 0x22776655)
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(process)
|
||||
sim.add_testbench(process)
|
||||
|
||||
def test_vcd_wrong_nonzero_time(self):
|
||||
s = Signal()
|
||||
|
|
@ -977,7 +1040,7 @@ class SimulatorRegressionTestCase(FHDLTestCase):
|
|||
sim = Simulator(Module())
|
||||
def process():
|
||||
self.assertEqual((yield -(Const(0b11, 2).as_signed())), 1)
|
||||
sim.add_process(process)
|
||||
sim.add_testbench(process)
|
||||
sim.run()
|
||||
|
||||
def test_bug_595(self):
|
||||
|
|
@ -1018,5 +1081,5 @@ class SimulatorRegressionTestCase(FHDLTestCase):
|
|||
self.assertEqual((yield C(0b0000, 4) | ~C(1, 1)), 0b0000)
|
||||
self.assertEqual((yield C(0b1111, 4) & ~C(1, 1)), 0b0000)
|
||||
self.assertEqual((yield C(0b1111, 4) ^ ~C(1, 1)), 0b1111)
|
||||
sim.add_process(process)
|
||||
sim.add_testbench(process)
|
||||
sim.run()
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue