vendor.xilinx_ultrascale: new supported family.
This commit is contained in:
whitequark
parent
bfd4538df0
commit
9fe27a15ad
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@ -47,6 +47,7 @@ nMigen can be used to target any FPGA or ASIC process that accepts behavioral Ve
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* Xilinx Spartan 3A (toolchains: ISE);
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* Xilinx Spartan 6 (toolchains: ISE);
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* Xilinx 7-series (toolchains: Vivado);
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* Xilinx UltraScale (toolchains: Vivado);
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* Intel (toolchains: Quartus).
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FOSS toolchains are listed in **bold**.
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422
nmigen/vendor/xilinx_ultrascale.py
vendored
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422
nmigen/vendor/xilinx_ultrascale.py
vendored
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@ -0,0 +1,422 @@
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from abc import abstractproperty
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from ..hdl import *
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from ..lib.cdc import ResetSynchronizer
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from ..build import *
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__all__ = ["XilinxUltraScalePlatform"]
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class XilinxUltraScalePlatform(TemplatedPlatform):
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"""
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Required tools:
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* ``vivado``
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The environment is populated by running the script specified in the environment variable
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``NMIGEN_ENV_Vivado``, if present.
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Available overrides:
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* ``script_after_read``: inserts commands after ``read_xdc`` in Tcl script.
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* ``script_after_synth``: inserts commands after ``synth_design`` in Tcl script.
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* ``script_after_place``: inserts commands after ``place_design`` in Tcl script.
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* ``script_after_route``: inserts commands after ``route_design`` in Tcl script.
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* ``script_before_bitstream``: inserts commands before ``write_bitstream`` in Tcl script.
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* ``script_after_bitstream``: inserts commands after ``write_bitstream`` in Tcl script.
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* ``add_constraints``: inserts commands in XDC file.
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* ``vivado_opts``: adds extra options for ``vivado``.
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Build products:
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* ``{{name}}.log``: Vivado log.
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* ``{{name}}_timing_synth.rpt``: Vivado report.
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* ``{{name}}_utilization_hierarchical_synth.rpt``: Vivado report.
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* ``{{name}}_utilization_synth.rpt``: Vivado report.
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* ``{{name}}_utilization_hierarchical_place.rpt``: Vivado report.
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* ``{{name}}_utilization_place.rpt``: Vivado report.
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* ``{{name}}_io.rpt``: Vivado report.
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* ``{{name}}_control_sets.rpt``: Vivado report.
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* ``{{name}}_clock_utilization.rpt``: Vivado report.
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* ``{{name}}_route_status.rpt``: Vivado report.
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* ``{{name}}_drc.rpt``: Vivado report.
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* ``{{name}}_timing.rpt``: Vivado report.
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* ``{{name}}_power.rpt``: Vivado report.
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* ``{{name}}_route.dcp``: Vivado design checkpoint.
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* ``{{name}}.bit``: binary bitstream with metadata.
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* ``{{name}}.bin``: binary bitstream.
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"""
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toolchain = "Vivado"
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device = abstractproperty()
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package = abstractproperty()
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speed = abstractproperty()
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grade = None
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required_tools = [
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"yosys",
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"vivado"
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]
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file_templates = {
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**TemplatedPlatform.build_script_templates,
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"build_{{name}}.sh": r"""
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# {{autogenerated}}
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set -e{{verbose("x")}}
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if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
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[ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}"
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{{emit_commands("sh")}}
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""",
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"{{name}}.v": r"""
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/* {{autogenerated}} */
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{{emit_verilog()}}
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""",
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"{{name}}.debug.v": r"""
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/* {{autogenerated}} */
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{{emit_debug_verilog()}}
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""",
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"{{name}}.tcl": r"""
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# {{autogenerated}}
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create_project -force -name {{name}} -part {{platform.device}}-{{platform.package}}-{{platform.speed}}{{"-" + platform.grade if platform.grade else ""}}
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{% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
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add_files {{file}}
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{% endfor %}
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add_files {{name}}.v
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read_xdc {{name}}.xdc
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{% for file in platform.iter_extra_files(".xdc") -%}
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read_xdc {{file}}
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{% endfor %}
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{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
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synth_design -top {{name}}
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foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.false_path == "TRUE"}] {
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set_false_path -to $cell
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}
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foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.max_delay != ""}] {
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set clock [get_clocks -of_objects \
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[all_fanin -flat -startpoints_only [get_pin $cell/D]]]
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if {[llength $clock] != 0} {
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set_max_delay -datapath_only -from $clock \
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-to [get_cells $cell] [get_property nmigen.vivado.max_delay $cell]
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}
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}
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{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
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report_timing_summary -file {{name}}_timing_synth.rpt
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report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
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report_utilization -file {{name}}_utilization_synth.rpt
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opt_design
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place_design
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{{get_override("script_after_place")|default("# (script_after_place placeholder)")}}
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report_utilization -hierarchical -file {{name}}_utilization_hierarchical_place.rpt
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report_utilization -file {{name}}_utilization_place.rpt
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report_io -file {{name}}_io.rpt
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report_control_sets -verbose -file {{name}}_control_sets.rpt
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report_clock_utilization -file {{name}}_clock_utilization.rpt
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route_design
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{{get_override("script_after_route")|default("# (script_after_route placeholder)")}}
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phys_opt_design
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report_timing_summary -no_header -no_detailed_paths
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write_checkpoint -force {{name}}_route.dcp
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report_route_status -file {{name}}_route_status.rpt
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report_drc -file {{name}}_drc.rpt
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report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
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report_power -file {{name}}_power.rpt
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{{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}
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write_bitstream -force -bin_file {{name}}.bit
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{{get_override("script_after_bitstream")|default("# (script_after_bitstream placeholder)")}}
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quit
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""",
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"{{name}}.xdc": r"""
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# {{autogenerated}}
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{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
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set_property LOC {{pin_name}} [get_ports {{port_name}}]
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{% for attr_name, attr_value in attrs.items() -%}
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set_property {{attr_name}} {{attr_value}} [get_ports {{port_name}}]
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{% endfor %}
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{% endfor %}
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{% for signal, frequency in platform.iter_clock_constraints() -%}
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create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
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{% endfor %}
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{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
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"""
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}
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command_templates = [
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r"""
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{{get_tool("vivado")}}
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{{verbose("-verbose")}}
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{{get_override("vivado_opts")|options}}
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-mode batch
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-log {{name}}.log
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-source {{name}}.tcl
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"""
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]
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def create_missing_domain(self, name):
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# Xilinx devices have a global write enable (GWE) signal that asserted during configuraiton
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# and deasserted once it ends. Because it is an asynchronous signal (GWE is driven by logic
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# syncronous to configuration clock, which is not used by most designs), even though it is
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# a low-skew global network, its deassertion may violate a setup/hold constraint with
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# relation to a user clock. The recommended solution is to use a BUFGCE driven by the EOS
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# signal. For details, see:
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# * https://www.xilinx.com/support/answers/44174.html
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# * https://www.xilinx.com/support/documentation/white_papers/wp272.pdf
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if name == "sync" and self.default_clk is not None:
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clk_i = self.request(self.default_clk).i
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if self.default_rst is not None:
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rst_i = self.request(self.default_rst).i
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m = Module()
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ready = Signal()
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m.submodules += Instance("STARTUPE3", o_EOS=ready)
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m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
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m.submodules += Instance("BUFGCE", i_CE=ready, i_I=clk_i, o_O=ClockSignal("sync"))
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if self.default_rst is not None:
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m.submodules.reset_sync = ResetSynchronizer(rst_i, domain="sync")
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return m
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def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
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def get_dff(clk, d, q):
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# SDR I/O is performed by packing a flip-flop into the pad IOB.
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for bit in range(len(q)):
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_q = Signal()
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_q.attrs["IOB"] = "TRUE"
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# Vivado 2019.1 seems to make this flip-flop ineligible for IOB packing unless
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# we prevent it from being optimized.
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_q.attrs["DONT_TOUCH"] = "TRUE"
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m.submodules += Instance("FDCE",
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i_C=clk,
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i_CE=Const(1),
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i_CLR=Const(0),
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i_D=d[bit],
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o_Q=_q
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)
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m.d.comb += q[bit].eq(_q)
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def get_iddr(clk, d, q1, q2):
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for bit in range(len(q1)):
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m.submodules += Instance("IDDRE1",
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p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
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p_IS_C_INVERTED=0, p_IS_CB_INVERTED=1,
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i_C=clk, i_CB=clk,
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i_R=Const(0),
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i_D=d[bit],
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o_Q1=q1[bit], o_Q2=q2[bit]
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)
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def get_oddr(clk, d1, d2, q):
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for bit in range(len(q)):
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m.submodules += Instance("ODDRE1",
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p_DDR_CLK_EDGE="SAME_EDGE",
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p_INIT=0,
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i_C=clk,
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i_SR=Const(0),
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i_D1=d1[bit], i_D2=d2[bit],
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o_Q=q[bit]
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)
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def get_ineg(y, invert):
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if invert:
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a = Signal.like(y, name_suffix="_n")
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m.d.comb += y.eq(~a)
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return a
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else:
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return y
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def get_oneg(a, invert):
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if invert:
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y = Signal.like(a, name_suffix="_n")
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m.d.comb += y.eq(~a)
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return y
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else:
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return a
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if "i" in pin.dir:
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if pin.xdr < 2:
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pin_i = get_ineg(pin.i, i_invert)
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elif pin.xdr == 2:
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pin_i0 = get_ineg(pin.i0, i_invert)
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pin_i1 = get_ineg(pin.i1, i_invert)
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = get_oneg(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = get_oneg(pin.o0, o_invert)
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pin_o1 = get_oneg(pin.o1, o_invert)
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i = o = t = None
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if "i" in pin.dir:
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i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
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if "o" in pin.dir:
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o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
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if pin.dir in ("oe", "io"):
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t = Signal(1, name="{}_xdr_t".format(pin.name))
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if pin.xdr == 0:
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if "i" in pin.dir:
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i = pin_i
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if "o" in pin.dir:
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o = pin_o
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if pin.dir in ("oe", "io"):
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t = ~pin.oe
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elif pin.xdr == 1:
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if "i" in pin.dir:
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get_dff(pin.i_clk, i, pin_i)
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if "o" in pin.dir:
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get_dff(pin.o_clk, pin_o, o)
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if pin.dir in ("oe", "io"):
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get_dff(pin.o_clk, ~pin.oe, t)
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elif pin.xdr == 2:
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if "i" in pin.dir:
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get_iddr(pin.i_clk, i, pin_i0, pin_i1)
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if "o" in pin.dir:
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get_oddr(pin.o_clk, pin_o0, pin_o1, o)
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if pin.dir in ("oe", "io"):
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get_dff(pin.o_clk, ~pin.oe, t)
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else:
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assert False
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return (i, o, t)
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
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i_I=port[bit],
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o_O=i[bit]
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)
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return m
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
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i_I=o[bit],
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o_O=port[bit]
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)
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return m
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def get_tristate(self, pin, port, attrs, invert):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFT",
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i_T=t,
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i_I=o[bit],
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o_O=port[bit]
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)
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return m
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
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i_T=t,
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i_I=o[bit],
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o_O=i[bit],
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io_IO=port[bit]
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)
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return m
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def get_diff_input(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
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for bit in range(len(p_port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUFDS",
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i_I=p_port[bit], i_IB=n_port[bit],
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o_O=i[bit]
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)
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return m
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def get_diff_output(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(len(p_port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFDS",
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i_I=o[bit],
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o_O=p_port[bit], o_OB=n_port[bit]
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)
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return m
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def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(len(p_port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFTDS",
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i_T=t,
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i_I=o[bit],
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o_O=p_port[bit], o_OB=n_port[bit]
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)
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return m
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def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
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for bit in range(len(p_port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUFDS",
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i_T=t,
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i_I=o[bit],
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o_O=i[bit],
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io_IO=p_port[bit], io_IOB=n_port[bit]
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)
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return m
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# The synchronizer implementations below apply two separate but related timing constraints.
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#
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# First, the ASYNC_REG attribute prevents inference of shift registers from synchronizer FFs,
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# and constraints the FFs to be placed as close as possible, ideally in one CLB. This attribute
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# only affects the synchronizer FFs themselves.
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#
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# Second, the nmigen.vivado.false_path or nmigen.vivado.max_delay attribute affects the path
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# into the synchronizer. If maximum input delay is specified, a datapath-only maximum delay
|
||||
# constraint is applied, limiting routing delay (and therefore skew) at the synchronizer input.
|
||||
# Otherwise, a false path constraint is used to omit the input path from the timing analysis.
|
||||
|
||||
def get_ff_sync(self, ff_sync):
|
||||
m = Module()
|
||||
flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index),
|
||||
reset=ff_sync._reset, reset_less=ff_sync._reset_less,
|
||||
attrs={"ASYNC_REG": "TRUE"})
|
||||
for index in range(ff_sync._stages)]
|
||||
if ff_sync._max_input_delay is None:
|
||||
flops[0].attrs["nmigen.vivado.false_path"] = "TRUE"
|
||||
else:
|
||||
flops[0].attrs["nmigen.vivado.max_delay"] = str(ff_sync._max_input_delay * 1e9)
|
||||
for i, o in zip((ff_sync.i, *flops), flops):
|
||||
m.d[ff_sync._o_domain] += o.eq(i)
|
||||
m.d.comb += ff_sync.o.eq(flops[-1])
|
||||
return m
|
||||
|
||||
def get_reset_sync(self, reset_sync):
|
||||
m = Module()
|
||||
m.domains += ClockDomain("reset_sync", async_reset=True, local=True)
|
||||
flops = [Signal(1, name="stage{}".format(index), reset=1,
|
||||
attrs={"ASYNC_REG": "TRUE"})
|
||||
for index in range(reset_sync._stages)]
|
||||
if reset_sync._max_input_delay is None:
|
||||
flops[0].attrs["nmigen.vivado.false_path"] = "TRUE"
|
||||
else:
|
||||
flops[0].attrs["nmigen.vivado.max_delay"] = str(reset_sync._max_input_delay * 1e9)
|
||||
for i, o in zip((0, *flops), flops):
|
||||
m.d.reset_sync += o.eq(i)
|
||||
m.d.comb += [
|
||||
ClockSignal("reset_sync").eq(ClockSignal(reset_sync._domain)),
|
||||
ResetSignal("reset_sync").eq(reset_sync.arst),
|
||||
ResetSignal(reset_sync._domain).eq(flops[-1])
|
||||
]
|
||||
return m
|
||||
Loading…
Reference in a new issue