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hdl.mem: tie rdport.en high for asynchronous or transparent ports.

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whitequark 2018-12-21 04:22:16 +00:00
parent 8d58cbf230
commit a061bfaa6c
3 changed files with 12 additions and 12 deletions
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1
examples/mem.py
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@ -17,7 +17,6 @@ class RegisterFile:
m.d.comb += [ m.d.comb += [
rdport.addr.eq(self.adr), rdport.addr.eq(self.adr),
self.dat_r.eq(rdport.data), self.dat_r.eq(rdport.data),
rdport.en.eq(1),
wrport.addr.eq(self.adr), wrport.addr.eq(self.adr),
wrport.data.eq(self.dat_w), wrport.data.eq(self.dat_w),
wrport.en.eq(self.we), wrport.en.eq(self.we),

2
nmigen/back/verilog.py
View file

@ -27,11 +27,9 @@ proc_init
proc_arst proc_arst
proc_dff proc_dff
proc_clean proc_clean
design -save orig
memory_collect memory_collect
write_verilog write_verilog
# Make sure there are no undriven wires in generated RTLIL. # Make sure there are no undriven wires in generated RTLIL.
design -load orig
proc proc
select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d
""".format(il_text)) """.format(il_text))

21
nmigen/hdl/mem.py
View file

@ -28,8 +28,8 @@ class Memory:
self.depth = depth self.depth = depth
self.init = None if init is None else list(init) self.init = None if init is None else list(init)
def read_port(self, domain="sync", asynchronous=False, transparent=True): def read_port(self, domain="sync", synchronous=False, transparent=True):
return ReadPort(self, domain, asynchronous, transparent) return ReadPort(self, domain, synchronous, transparent)
def write_port(self, domain="sync", priority=0, granularity=None): def write_port(self, domain="sync", priority=0, granularity=None):
if granularity is None: if granularity is None:
@ -42,22 +42,25 @@ class Memory:
class ReadPort: class ReadPort:
def __init__(self, memory, domain, asynchronous, transparent): def __init__(self, memory, domain, synchronous, transparent):
self.memory = memory self.memory = memory
self.domain = domain self.domain = domain
self.asynchronous = asynchronous self.synchronous = synchronous
self.transparent = transparent self.transparent = transparent
self.addr = Signal(max=memory.depth) self.addr = Signal(max=memory.depth)
self.data = Signal(memory.width) self.data = Signal(memory.width)
self.en = Signal() if synchronous and transparent:
self.en = Signal()
else:
self.en = Const(1)
def get_fragment(self, platform): def get_fragment(self, platform):
return Instance("$memrd", return Instance("$memrd",
p_MEMID=self.memory, p_MEMID=self.memory,
p_ABITS=self.addr.nbits, p_ABITS=self.addr.nbits,
p_WIDTH=self.data.nbits, p_WIDTH=self.data.nbits,
p_CLK_ENABLE=not self.asynchronous, p_CLK_ENABLE=self.synchronous,
p_CLK_POLARITY=1, p_CLK_POLARITY=1,
p_TRANSPARENT=self.transparent, p_TRANSPARENT=self.transparent,
i_CLK=ClockSignal(self.domain), i_CLK=ClockSignal(self.domain),