lib.cdc: use a local clock domain in ResetSynchronizer.

This reverts commit 779f3ee906.
This reverts commit 300d47ca2e.
This reverts commit 9c54d0c061.

nmigen/back/pysim.py

@@ -10,9 +10,6 @@ from ..tools import flatten
 from ..hdl.ast import *
 from ..hdl.ir import *
 from ..hdl.xfrm import ValueVisitor, StatementVisitor
-from ..hdl.ast import DUID
-from ..hdl.dsl import Module
-from ..hdl.cd import ClockDomain
 
 
 __all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]
@@ -359,24 +356,9 @@ class _StatementCompiler(StatementVisitor):
         return run
 
 
-class _SimulatorPlatform:
-    def get_reset_sync(self, reset_sync):
-        m = Module()
-        cd = ClockDomain("_reset_sync_{}".format(DUID().duid), async_reset=True)
-        m.domains += cd
-        for i, o in zip((0, *reset_sync._regs), reset_sync._regs):
-            m.d[cd.name] += o.eq(i)
-        m.d.comb += [
-            ClockSignal(cd.name).eq(ClockSignal(reset_sync.domain)),
-            ResetSignal(cd.name).eq(reset_sync.arst),
-            ResetSignal(reset_sync.domain).eq(reset_sync._regs[-1])
-        ]
-        return m
-
-
 class Simulator:
     def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
-        self._fragment        = Fragment.get(fragment, platform=_SimulatorPlatform())
+        self._fragment        = Fragment.get(fragment, platform=None)
 
         self._signal_slots    = SignalDict()  # Signal -> int/slot
         self._slot_signals    = list()        # int/slot -> Signal

nmigen/lib/cdc.py

@@ -82,16 +82,12 @@ class ResetSynchronizer(Elaboratable):
             return platform.get_reset_sync(self)
 
         m = Module()
-        for i, o in zip((Const(0, 1), *self._regs), self._regs):
-            m.submodules += Instance("$adff",
-                p_CLK_POLARITY=1,
-                p_ARST_POLARITY=1,
-                p_ARST_VALUE=Const(1, 1),
-                p_WIDTH=1,
-                i_CLK=ClockSignal(self.domain),
-                i_ARST=self.arst,
-                i_D=i,
-                o_Q=o
-            )
-        m.d.comb += ResetSignal(self.domain).eq(self._regs[-1])
+        m.domains += ClockDomain("reset_sync", async_reset=True, local=True)
+        for i, o in zip((0, *self._regs), self._regs):
+            m.d.reset_sync += o.eq(i)
+        m.d.comb += [
+            ClockSignal("reset_sync").eq(ClockSignal(self.domain)),
+            ResetSignal("reset_sync").eq(self.arst),
+            ResetSignal(self.domain).eq(self._regs[-1])
+        ]
         return m