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lib.cdc: use a local clock domain in ResetSynchronizer.

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This reverts commit 779f3ee906.
This reverts commit 300d47ca2e.
This reverts commit 9c54d0c061.
This commit is contained in:
whitequark 2019-08-19 20:47:40 +00:00
parent 71ee64c403
commit a069d975b2
2 changed files with 9 additions and 31 deletions
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20
nmigen/back/pysim.py
View file

@ -10,9 +10,6 @@ from ..tools import flatten
from ..hdl.ast import * from ..hdl.ast import *
from ..hdl.ir import * from ..hdl.ir import *
from ..hdl.xfrm import ValueVisitor, StatementVisitor from ..hdl.xfrm import ValueVisitor, StatementVisitor
from ..hdl.ast import DUID
from ..hdl.dsl import Module
from ..hdl.cd import ClockDomain
__all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"] __all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]
@ -359,24 +356,9 @@ class _StatementCompiler(StatementVisitor):
return run return run
class _SimulatorPlatform:
def get_reset_sync(self, reset_sync):
m = Module()
cd = ClockDomain("_reset_sync_{}".format(DUID().duid), async_reset=True)
m.domains += cd
for i, o in zip((0, *reset_sync._regs), reset_sync._regs):
m.d[cd.name] += o.eq(i)
m.d.comb += [
ClockSignal(cd.name).eq(ClockSignal(reset_sync.domain)),
ResetSignal(cd.name).eq(reset_sync.arst),
ResetSignal(reset_sync.domain).eq(reset_sync._regs[-1])
]
return m
class Simulator: class Simulator:
def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()): def __init__(self, fragment, vcd_file=None, gtkw_file=None, traces=()):
self._fragment = Fragment.get(fragment, platform=_SimulatorPlatform()) self._fragment = Fragment.get(fragment, platform=None)
self._signal_slots = SignalDict() # Signal -> int/slot self._signal_slots = SignalDict() # Signal -> int/slot
self._slot_signals = list() # int/slot -> Signal self._slot_signals = list() # int/slot -> Signal

20
nmigen/lib/cdc.py
View file

@ -82,16 +82,12 @@ class ResetSynchronizer(Elaboratable):
return platform.get_reset_sync(self) return platform.get_reset_sync(self)
m = Module() m = Module()
for i, o in zip((Const(0, 1), *self._regs), self._regs): m.domains += ClockDomain("reset_sync", async_reset=True, local=True)
m.submodules += Instance("$adff", for i, o in zip((0, *self._regs), self._regs):
p_CLK_POLARITY=1, m.d.reset_sync += o.eq(i)
p_ARST_POLARITY=1, m.d.comb += [
p_ARST_VALUE=Const(1, 1), ClockSignal("reset_sync").eq(ClockSignal(self.domain)),
p_WIDTH=1, ResetSignal("reset_sync").eq(self.arst),
i_CLK=ClockSignal(self.domain), ResetSignal(self.domain).eq(self._regs[-1])
i_ARST=self.arst, ]
i_D=i,
o_Q=o
)
m.d.comb += ResetSignal(self.domain).eq(self._regs[-1])
return m return m