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vendor._intel: use dff instead of $dff.

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Fixes #1046.
This commit is contained in:
Wanda 2024-02-13 06:57:22 +01:00 committed by Catherine
parent 3867623727
commit a0c8b18546
1 changed files with 26 additions and 21 deletions
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47
amaranth/vendor/_intel.py
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@ -312,13 +312,15 @@ class IntelPlatform(TemplatedPlatform):
return get_ineg(pin.i) return get_ineg(pin.i)
elif pin.xdr == 1: elif pin.xdr == 1:
i_sdr = Signal(pin.width, name="{}_i_sdr") i_sdr = Signal(pin.width, name="{}_i_sdr")
m.submodules += Instance("$dff", i_neg = get_ineg(pin.i)
p_CLK_POLARITY=1, for bit in range(pin.width):
p_WIDTH=pin.width, m.submodules += Instance("dff",
i_CLK=pin.i_clk, i_clk=pin.i_clk,
i_D=i_sdr, i_d=i_sdr[bit],
o_Q=get_ineg(pin.i), o_q=i_neg[bit],
) o_clrn=Const(1),
o_prn=Const(1),
)
return i_sdr return i_sdr
elif pin.xdr == 2: elif pin.xdr == 2:
i_ddr = Signal(pin.width, name=f"{pin.name}_i_ddr") i_ddr = Signal(pin.width, name=f"{pin.name}_i_ddr")
@ -346,13 +348,15 @@ class IntelPlatform(TemplatedPlatform):
return get_oneg(pin.o) return get_oneg(pin.o)
elif pin.xdr == 1: elif pin.xdr == 1:
o_sdr = Signal(pin.width, name=f"{pin.name}_o_sdr") o_sdr = Signal(pin.width, name=f"{pin.name}_o_sdr")
m.submodules += Instance("$dff", for bit in range(pin.width):
p_CLK_POLARITY=1, o_neg = get_oneg(pin.o)
p_WIDTH=pin.width, m.submodules += Instance("dff",
i_CLK=pin.o_clk, i_clk=pin.o_clk,
i_D=get_oneg(pin.o), i_d=o_neg[bit],
o_Q=o_sdr, o_q=o_sdr[bit],
) o_clrn=Const(1),
o_prn=Const(1),
)
return o_sdr return o_sdr
elif pin.xdr == 2: elif pin.xdr == 2:
o_ddr = Signal(pin.width, name=f"{pin.name}_o_ddr") o_ddr = Signal(pin.width, name=f"{pin.name}_o_ddr")
@ -374,13 +378,14 @@ class IntelPlatform(TemplatedPlatform):
elif pin.xdr in (1, 2): elif pin.xdr in (1, 2):
oe_reg = Signal(pin.width, name=f"{pin.name}_oe_reg") oe_reg = Signal(pin.width, name=f"{pin.name}_oe_reg")
oe_reg.attrs["useioff"] = "1" oe_reg.attrs["useioff"] = "1"
m.submodules += Instance("$dff", for bit in range(pin.width):
p_CLK_POLARITY=1, m.submodules += Instance("dff",
p_WIDTH=pin.width, i_clk=pin.o_clk,
i_CLK=pin.o_clk, i_d=pin.oe,
i_D=pin.oe, o_q=oe_reg[bit],
o_Q=oe_reg, o_clrn=Const(1),
) o_prn=Const(1),
)
return oe_reg return oe_reg
assert False assert False