back.{rtlil,verilog}: split convert_fragment() off convert().

Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.

nmigen/compat/fhdl/verilog.py

@@ -21,7 +21,7 @@ def convert(fi, ios=None, name="top", special_overrides=dict(),
         if create_clock_domains:
             return ClockDomain(name)
     v_output = verilog.convert(
-        fragment=Fragment.get(fi.get_fragment(), platform=None),
+        elaboratable=fi.get_fragment(),
         name=name,
         ports=ios or (),
         missing_domain=missing_domain