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build.dsl: allow both str and int resource attributes.

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This commit is contained in:
whitequark 2019-08-30 08:35:52 +00:00
parent 98278a044d
commit a4b58cbf3a
2 changed files with 10 additions and 11 deletions
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9
nmigen/build/dsl.py
View file

@ -92,8 +92,9 @@ def DiffPairsN(*args, **kwargs):
class Attrs(OrderedDict):
def __init__(self, **attrs):
for key, value in attrs.items():
if not (value is None or isinstance(value, str) or hasattr(value, "__call__")):
raise TypeError("Value of attribute {} must be None, str, or callable, not {!r}"
if not (value is None or isinstance(value, (str, int)) or hasattr(value, "__call__")):
raise TypeError("Value of attribute {} must be None, int, str, or callable, "
"not {!r}"
.format(key, value))
super().__init__(**attrs)
@ -103,10 +104,8 @@ class Attrs(OrderedDict):
for key, value in self.items():
if value is None:
items.append("!" + key)
elif hasattr(value, "__call__"):
items.append(key + "=" + repr(value))
else:
items.append(key + "=" + value)
items.append(key + "=" + repr(value))
return "(attrs {})".format(" ".join(items))

12
nmigen/test/test_build_dsl.py
View file

@ -109,9 +109,9 @@ class DiffPairsTestCase(FHDLTestCase):
class AttrsTestCase(FHDLTestCase):
def test_basic(self):
a = Attrs(IO_STANDARD="LVCMOS33", PULLUP="1")
a = Attrs(IO_STANDARD="LVCMOS33", PULLUP=1)
self.assertEqual(a["IO_STANDARD"], "LVCMOS33")
self.assertEqual(repr(a), "(attrs IO_STANDARD=LVCMOS33 PULLUP=1)")
self.assertEqual(repr(a), "(attrs IO_STANDARD='LVCMOS33' PULLUP=1)")
def test_remove(self):
a = Attrs(FOO=None)
@ -126,8 +126,8 @@ class AttrsTestCase(FHDLTestCase):
def test_wrong_value(self):
with self.assertRaises(TypeError,
msg="Value of attribute FOO must be None, str, or callable, not 1"):
a = Attrs(FOO=1)
msg="Value of attribute FOO must be None, int, str, or callable, not 1.0"):
a = Attrs(FOO=1.0)
class ClockTestCase(FHDLTestCase):
@ -142,7 +142,7 @@ class SubsignalTestCase(FHDLTestCase):
def test_basic_pins(self):
s = Subsignal("a", Pins("A0"), Attrs(IOSTANDARD="LVCMOS33"))
self.assertEqual(repr(s),
"(subsignal a (pins io A0) (attrs IOSTANDARD=LVCMOS33))")
"(subsignal a (pins io A0) (attrs IOSTANDARD='LVCMOS33'))")
def test_basic_diffpairs(self):
s = Subsignal("a", DiffPairs("A0", "B0"))
@ -223,7 +223,7 @@ class ResourceTestCase(FHDLTestCase):
self.assertEqual(repr(r), "(resource serial 0"
" (subsignal tx (pins o A0))"
" (subsignal rx (pins i A1))"
" (attrs IOSTANDARD=LVCMOS33))")
" (attrs IOSTANDARD='LVCMOS33'))")
def test_family(self):
ios = [Subsignal("clk", Pins("A0", dir="o"))]