hdl.ir: resolve hierarchy conflicts before creating missing domains.
Otherwise, code such as:
m.submodules.a = (something with cd_sync)
m.submodules.b = (something with cd_sync)
m.d.b_sync += x.eq(y)
causes an assertion failure.
Fixes #304 (again).
This commit is contained in:
parent
7cb3095334
commit
a7be3b480a
2 changed files with 29 additions and 2 deletions
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@ -203,6 +203,15 @@ class Fragment:
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driver_subfrags = SignalDict()
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memory_subfrags = OrderedDict()
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def add_subfrag(registry, entity, entry):
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# Because of missing domain insertion, at the point when this code runs, we have
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# a mixture of bound and unbound {Clock,Reset}Signals. Map the bound ones to
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# the actual signals (because the signal itself can be driven as well); but leave
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# the unbound ones as it is, because there's no concrete signal for it yet anyway.
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if isinstance(entity, ClockSignal) and entity.domain in self.domains:
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entity = self.domains[entity.domain].clk
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elif isinstance(entity, ResetSignal) and entity.domain in self.domains:
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entity = self.domains[entity.domain].rst
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if entity not in registry:
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registry[entity] = set()
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registry[entity].add(entry)
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@ -387,12 +396,15 @@ class Fragment:
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"requested domain '{}' (defines {})."
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.format(domain_name, ", ".join("'{}'".format(n) for n in defined)))
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self.add_subfragment(new_fragment, "cd_{}".format(domain_name))
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self.add_domains(new_fragment.domains.values())
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return new_domains
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def _propagate_domains(self, missing_domain):
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new_domains = self.create_missing_domains(missing_domain)
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self._propagate_domains_up()
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self._propagate_domains_down()
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self._resolve_hierarchy_conflicts()
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new_domains = self.create_missing_domains(missing_domain)
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self._propagate_domains_down()
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return new_domains
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def _prepare_use_def_graph(self, parent, level, uses, defs, ios, top):
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@ -543,7 +555,6 @@ class Fragment:
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fragment = SampleLowerer()(self)
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new_domains = fragment._propagate_domains(missing_domain)
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fragment = DomainLowerer()(fragment)
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fragment._resolve_hierarchy_conflicts()
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if ports is None:
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fragment._propagate_ports(ports=(), all_undef_as_ports=True)
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else:
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