hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.

Fixes #125.
This commit is contained in:
whitequark 2019-07-08 10:26:49 +00:00
parent 345a26b04b
commit a7fbff94d8
8 changed files with 45 additions and 0 deletions

View file

@ -693,6 +693,8 @@ class ClockSignal(Value):
super().__init__(src_loc_at=src_loc_at)
if not isinstance(domain, str):
raise TypeError("Clock domain name must be a string, not '{!r}'".format(domain))
if domain == "comb":
raise ValueError("Domain '{}' does not have a clock".format(domain))
self.domain = domain
def shape(self):
@ -727,6 +729,8 @@ class ResetSignal(Value):
super().__init__(src_loc_at=src_loc_at)
if not isinstance(domain, str):
raise TypeError("Clock domain name must be a string, not '{!r}'".format(domain))
if domain == "comb":
raise ValueError("Domain '{}' does not have a reset".format(domain))
self.domain = domain
self.allow_reset_less = allow_reset_less

View file

@ -50,6 +50,8 @@ class ClockDomain:
raise ValueError("Clock domain name must be specified explicitly")
if name.startswith("cd_"):
name = name[3:]
if name == "comb":
raise ValueError("Domain '{}' may not be clocked".format(name))
self.name = name
self.clk = Signal(name=self._name_for(name, "clk"), src_loc_at=1)

View file

@ -261,6 +261,8 @@ class Module(_ModuleBuilderRoot, Elaboratable):
@contextmanager
def FSM(self, reset=None, domain="sync", name="fsm"):
self._check_context("FSM", context=None)
if domain == "comb":
raise ValueError("FSM may not be driven by the '{}' domain".format(domain))
fsm_data = self._set_ctrl("FSM", {
"name": name,
"signal": Signal(name="{}_state".format(name), src_loc_at=2),

View file

@ -326,6 +326,11 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer)
def __init__(self, domain_map):
if isinstance(domain_map, str):
domain_map = {"sync": domain_map}
for src, dst in domain_map.items():
if src == "comb":
raise ValueError("Domain '{}' may not be renamed".format(src))
if dst == "comb":
raise ValueError("Domain '{}' may not be renamed to '{}'".format(src, dst))
self.domain_map = OrderedDict(domain_map)
def on_ClockSignal(self, value):