hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.

Fixes #125.
This commit is contained in:
whitequark 2019-07-08 10:26:49 +00:00
parent 345a26b04b
commit a7fbff94d8
8 changed files with 45 additions and 0 deletions

View file

@ -515,6 +515,11 @@ class ClockSignalTestCase(FHDLTestCase):
s1 = ClockSignal()
self.assertEqual(repr(s1), "(clk sync)")
def test_wrong_name_comb(self):
with self.assertRaises(ValueError,
msg="Domain 'comb' does not have a clock"):
ClockSignal("comb")
class ResetSignalTestCase(FHDLTestCase):
def test_domain(self):
@ -534,6 +539,11 @@ class ResetSignalTestCase(FHDLTestCase):
s1 = ResetSignal()
self.assertEqual(repr(s1), "(rst sync)")
def test_wrong_name_comb(self):
with self.assertRaises(ValueError,
msg="Domain 'comb' does not have a reset"):
ResetSignal("comb")
class MockUserValue(UserValue):
def __init__(self, lowered):

View file

@ -55,3 +55,8 @@ class ClockDomainTestCase(FHDLTestCase):
sync.rename("pix")
self.assertEqual(sync.name, "pix")
self.assertEqual(sync.clk.name, "pix_clk")
def test_wrong_name_comb(self):
with self.assertRaises(ValueError,
msg="Domain 'comb' may not be clocked"):
comb = ClockDomain()

View file

@ -458,6 +458,13 @@ class DSLTestCase(FHDLTestCase):
()
""")
def test_FSM_wrong_domain(self):
m = Module()
with self.assertRaises(ValueError,
msg="FSM may not be driven by the 'comb' domain"):
with m.FSM(domain="comb"):
pass
def test_FSM_wrong_redefined(self):
m = Module()
with m.FSM():

View file

@ -88,6 +88,16 @@ class DomainRenamerTestCase(FHDLTestCase):
"pix": cd_pix,
})
def test_rename_wrong_to_comb(self):
with self.assertRaises(ValueError,
msg="Domain 'sync' may not be renamed to 'comb'"):
DomainRenamer("comb")
def test_rename_wrong_from_comb(self):
with self.assertRaises(ValueError,
msg="Domain 'comb' may not be renamed"):
DomainRenamer({"comb": "sync"})
class DomainLowererTestCase(FHDLTestCase):
def setUp(self):