build.dsl: replace extras= with Attrs().
This change proved more tricky than expected due to downstream dependencies, so it also includes some secondary refactoring.
This commit is contained in:
whitequark
parent
c52cd72d3e
commit
ab3f103e5a
7 changed files with 262 additions and 253 deletions
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@ -1,3 +1,3 @@
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from .dsl import Pins, DiffPairs, Subsignal, Resource, Connector
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from .res import ConstraintError
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from .dsl import Pins, DiffPairs, Attrs, Subsignal, Resource, Connector
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from .res import ResourceError
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from .plat import Platform, TemplatedPlatform
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@ -1,7 +1,7 @@
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from collections import OrderedDict
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__all__ = ["Pins", "DiffPairs", "Subsignal", "Resource", "Connector"]
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__all__ = ["Pins", "DiffPairs", "Attrs", "Subsignal", "Resource", "Connector"]
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class Pins:
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@ -32,13 +32,15 @@ class Pins:
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return iter(self.names)
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def map_names(self, mapping, resource):
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mapped_names = []
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for name in self.names:
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while ":" in name:
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if name not in mapping:
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raise NameError("Resource {!r} refers to nonexistent connector pin {}"
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.format(resource, name))
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name = mapping[name]
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yield name
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mapped_names.append(name)
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return mapped_names
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def __repr__(self):
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return "(pins {} {})".format(self.dir, " ".join(self.names))
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@ -67,65 +69,66 @@ class DiffPairs:
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self.dir, " ".join(self.p.names), " ".join(self.n.names))
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class Attrs(OrderedDict):
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def __init__(self, **attrs):
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for attr_key, attr_value in attrs.items():
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if not isinstance(attr_value, str):
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raise TypeError("Attribute value must be a string, not {!r}"
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.format(attr_value))
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super().__init__(**attrs)
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def __repr__(self):
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return "(attrs {})".format(" ".join("{}={}".format(k, v)
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for k, v in self.items()))
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class Subsignal:
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def __init__(self, name, *io, extras=None):
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self.name = name
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def __init__(self, name, *args):
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self.name = name
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self.ios = []
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self.attrs = Attrs()
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if not io:
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raise TypeError("Missing I/O constraints")
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for c in io:
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if not isinstance(c, (Pins, DiffPairs, Subsignal)):
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raise TypeError("I/O constraint must be one of Pins, DiffPairs or Subsignal, "
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"not {!r}"
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.format(c))
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if isinstance(io[0], (Pins, DiffPairs)) and len(io) > 1:
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raise TypeError("Pins and DiffPairs cannot be followed by more I/O constraints, but "
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"{!r} is followed by {!r}"
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.format(io[0], io[1]))
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if isinstance(io[0], Subsignal):
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for c in io[1:]:
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if not isinstance(c, Subsignal):
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raise TypeError("A Subsignal can only be followed by more Subsignals, but "
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"{!r} is followed by {!r}"
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.format(io[0], c))
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self.io = io
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self.extras = {}
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if extras is not None:
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if not isinstance(extras, dict):
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raise TypeError("Extra constraints must be a dict, not {!r}"
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.format(extras))
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for extra_key, extra_value in extras.items():
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if not isinstance(extra_key, str):
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raise TypeError("Extra constraint key must be a string, not {!r}"
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.format(extra_key))
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if not isinstance(extra_value, str):
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raise TypeError("Extra constraint value must be a string, not {!r}"
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.format(extra_value))
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self.extras[extra_key] = extra_value
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if isinstance(self.io[0], Subsignal):
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for sub in self.io:
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sub.extras.update(self.extras)
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if not args:
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raise ValueError("Missing I/O constraints")
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for arg in args:
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if isinstance(arg, (Pins, DiffPairs)):
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if not self.ios:
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self.ios.append(arg)
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else:
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raise TypeError("Pins and DiffPairs are incompatible with other location or "
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"subsignal constraints, but {!r} appears after {!r}"
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.format(arg, self.ios[-1]))
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elif isinstance(arg, Subsignal):
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if not self.ios or isinstance(self.ios[-1], Subsignal):
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self.ios.append(arg)
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else:
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raise TypeError("Subsignal is incompatible with location constraints, but "
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"{!r} appears after {!r}"
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.format(arg, self.ios[-1]))
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elif isinstance(arg, Attrs):
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self.attrs.update(arg)
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else:
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raise TypeError("I/O constraint must be one of Pins, DiffPairs, Subsignal, "
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"or Attrs, not {!r}"
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.format(arg))
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def __repr__(self):
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return "(subsignal {} {} {})".format(self.name,
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" ".join(map(repr, self.io)),
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" ".join("{}={}".format(k, v)
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for k, v in self.extras.items()))
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" ".join(map(repr, self.ios)),
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repr(self.attrs))
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class Resource(Subsignal):
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def __init__(self, name, number, *io, extras=None):
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super().__init__(name, *io, extras=extras)
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def __init__(self, name, number, *args):
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super().__init__(name, *args)
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self.number = number
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def __repr__(self):
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return "(resource {} {} {} {})".format(self.name, self.number,
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" ".join(map(repr, self.io)),
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" ".join("{}={}".format(k, v)
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for k, v in self.extras.items()))
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" ".join(map(repr, self.ios)),
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repr(self.attrs))
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class Connector:
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@ -17,7 +17,7 @@ from .run import *
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__all__ = ["Platform", "TemplatedPlatform"]
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class Platform(ConstraintManager, metaclass=ABCMeta):
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class Platform(ResourceManager, metaclass=ABCMeta):
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resources = abstractproperty()
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connectors = abstractproperty()
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clocks = abstractproperty()
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@ -67,25 +67,25 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
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pin_fragment.flatten = True
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fragment.add_subfragment(pin_fragment, name="pin_{}".format(pin.name))
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for pin, port, extras in self.iter_single_ended_pins():
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for pin, port, attrs in self.iter_single_ended_pins():
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if pin.dir == "i":
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add_pin_fragment(pin, self.get_input(pin, port, extras))
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add_pin_fragment(pin, self.get_input(pin, port, attrs))
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if pin.dir == "o":
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add_pin_fragment(pin, self.get_output(pin, port, extras))
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add_pin_fragment(pin, self.get_output(pin, port, attrs))
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if pin.dir == "oe":
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add_pin_fragment(pin, self.get_tristate(pin, port, extras))
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add_pin_fragment(pin, self.get_tristate(pin, port, attrs))
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if pin.dir == "io":
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add_pin_fragment(pin, self.get_input_output(pin, port, extras))
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add_pin_fragment(pin, self.get_input_output(pin, port, attrs))
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for pin, p_port, n_port, extras in self.iter_differential_pins():
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for pin, p_port, n_port, attrs in self.iter_differential_pins():
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if pin.dir == "i":
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add_pin_fragment(pin, self.get_diff_input(pin, p_port, n_port, extras))
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add_pin_fragment(pin, self.get_diff_input(pin, p_port, n_port, attrs))
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if pin.dir == "o":
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add_pin_fragment(pin, self.get_diff_output(pin, p_port, n_port, extras))
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add_pin_fragment(pin, self.get_diff_output(pin, p_port, n_port, attrs))
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if pin.dir == "oe":
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add_pin_fragment(pin, self.get_diff_tristate(pin, p_port, n_port, extras))
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add_pin_fragment(pin, self.get_diff_tristate(pin, p_port, n_port, attrs))
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if pin.dir == "io":
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add_pin_fragment(pin, self.get_diff_input_output(pin, p_port, n_port, extras))
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add_pin_fragment(pin, self.get_diff_input_output(pin, p_port, n_port, attrs))
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return self.toolchain_prepare(fragment, name, **kwargs)
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@ -104,7 +104,7 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
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raise NotImplementedError("Platform {} does not support programming"
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.format(self.__class__.__name__))
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def _check_feature(self, feature, pin, extras, valid_xdrs, valid_extras):
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def _check_feature(self, feature, pin, attrs, valid_xdrs, valid_attrs):
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if not valid_xdrs:
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raise NotImplementedError("Platform {} does not support {}"
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.format(self.__class__.__name__, feature))
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@ -112,29 +112,29 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
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raise NotImplementedError("Platform {} does not support {} for XDR {}"
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.format(self.__class__.__name__, feature, pin.xdr))
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if not valid_extras and extras:
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raise NotImplementedError("Platform {} does not support extras for {}"
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if not valid_attrs and attrs:
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raise NotImplementedError("Platform {} does not support attributes for {}"
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.format(self.__class__.__name__, feature))
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def get_input(self, pin, port, extras):
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self._check_feature("single-ended input", pin, extras,
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valid_xdrs=(0,), valid_extras=None)
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def get_input(self, pin, port, attrs):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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m = Module()
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m.d.comb += pin.i.eq(port)
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return m
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def get_output(self, pin, port, extras):
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self._check_feature("single-ended output", pin, extras,
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valid_xdrs=(0,), valid_extras=None)
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def get_output(self, pin, port, attrs):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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m = Module()
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m.d.comb += port.eq(pin.o)
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return m
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def get_tristate(self, pin, port, extras):
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self._check_feature("single-ended tristate", pin, extras,
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valid_xdrs=(0,), valid_extras=None)
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def get_tristate(self, pin, port, attrs):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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m = Module()
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m.submodules += Instance("$tribuf",
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@ -145,9 +145,9 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
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)
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return m
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def get_input_output(self, pin, port, extras):
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self._check_feature("single-ended input/output", pin, extras,
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valid_xdrs=(0,), valid_extras=None)
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def get_input_output(self, pin, port, attrs):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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m = Module()
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m.submodules += Instance("$tribuf",
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@ -159,21 +159,21 @@ class Platform(ConstraintManager, metaclass=ABCMeta):
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m.d.comb += pin.i.eq(port)
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return m
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def get_diff_input(self, pin, p_port, n_port, extras):
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self._check_feature("differential input", pin, extras,
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valid_xdrs=(), valid_extras=None)
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def get_diff_input(self, pin, p_port, n_port, attrs):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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def get_diff_output(self, pin, p_port, n_port, extras):
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self._check_feature("differential output", pin, extras,
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valid_xdrs=(), valid_extras=None)
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def get_diff_output(self, pin, p_port, n_port, attrs):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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def get_diff_tristate(self, pin, p_port, n_port, extras):
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self._check_feature("differential tristate", pin, extras,
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valid_xdrs=(), valid_extras=None)
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def get_diff_tristate(self, pin, p_port, n_port, attrs):
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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def get_diff_input_output(self, pin, p_port, n_port, extras):
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self._check_feature("differential input/output", pin, extras,
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valid_xdrs=(), valid_extras=None)
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def get_diff_input_output(self, pin, p_port, n_port, attrs):
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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class TemplatedPlatform(Platform):
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@ -7,21 +7,24 @@ from ..lib.io import *
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from .dsl import *
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__all__ = ["ConstraintError", "ConstraintManager"]
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__all__ = ["ResourceError", "ResourceManager"]
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class ConstraintError(Exception):
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class ResourceError(Exception):
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pass
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class ConstraintManager:
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class ResourceManager:
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def __init__(self, resources, connectors, clocks):
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self.resources = OrderedDict()
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self._requested = OrderedDict()
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self.connectors = OrderedDict()
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self._conn_pins = OrderedDict()
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self.clocks = OrderedDict()
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self._mapping = OrderedDict()
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self._requested = OrderedDict()
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# Constraint lists
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self._ports = []
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self.add_resources(resources)
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@ -50,36 +53,36 @@ class ConstraintManager:
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self.connectors[conn.name, conn.number] = conn
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for conn_pin, plat_pin in conn:
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assert conn_pin not in self._mapping
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self._mapping[conn_pin] = plat_pin
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assert conn_pin not in self._conn_pins
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self._conn_pins[conn_pin] = plat_pin
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def add_clock(self, name, number, frequency):
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resource = self.lookup(name, number)
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if isinstance(resource.io[0], Subsignal):
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if isinstance(resource.ios[0], Subsignal):
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raise TypeError("Cannot constrain frequency of resource {}#{} because it has "
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"subsignals"
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.format(resource.name, resource.number, frequency))
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if (resource.name, resource.number) in self.clocks:
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other = self.clocks[resource.name, resource.number]
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raise ConstraintError("Resource {}#{} is already constrained to a frequency of "
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"{:f} MHz"
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.format(resource.name, resource.number, other / 1e6))
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raise ResourceError("Resource {}#{} is already constrained to a frequency of "
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"{:f} MHz"
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.format(resource.name, resource.number, other / 1e6))
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self.clocks[resource.name, resource.number] = frequency
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def lookup(self, name, number=0):
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if (name, number) not in self.resources:
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raise ConstraintError("Resource {}#{} does not exist"
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raise ResourceError("Resource {}#{} does not exist"
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.format(name, number))
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return self.resources[name, number]
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def request(self, name, number=0, *, dir=None, xdr=None):
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resource = self.lookup(name, number)
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if (resource.name, resource.number) in self._requested:
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raise ConstraintError("Resource {}#{} has already been requested"
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.format(name, number))
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raise ResourceError("Resource {}#{} has already been requested"
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.format(name, number))
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def merge_options(subsignal, dir, xdr):
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if isinstance(subsignal.io[0], Subsignal):
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if isinstance(subsignal.ios[0], Subsignal):
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if dir is None:
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dir = dict()
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if xdr is None:
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@ -92,52 +95,54 @@ class ConstraintManager:
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raise TypeError("Data rate must be a dict, not {!r}, because {!r} "
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"has subsignals"
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.format(xdr, subsignal))
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for sub in subsignal.io:
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for sub in subsignal.ios:
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sub_dir = dir.get(sub.name, None)
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sub_xdr = xdr.get(sub.name, None)
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dir[sub.name], xdr[sub.name] = merge_options(sub, sub_dir, sub_xdr)
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else:
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if dir is None:
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dir = subsignal.io[0].dir
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dir = subsignal.ios[0].dir
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if xdr is None:
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xdr = 0
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if dir not in ("i", "o", "oe", "io", "-"):
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raise TypeError("Direction must be one of \"i\", \"o\", \"oe\", \"io\", "
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"or \"-\", not {!r}"
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.format(dir))
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if dir != subsignal.io[0].dir and not (subsignal.io[0].dir == "io" or dir == "-"):
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if dir != subsignal.ios[0].dir and \
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not (subsignal.ios[0].dir == "io" or dir == "-"):
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raise ValueError("Direction of {!r} cannot be changed from \"{}\" to \"{}\"; "
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"direction can be changed from \"io\" to \"i\", \"o\", or "
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"\"oe\", or from anything to \"-\""
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.format(subsignal.io[0], subsignal.io[0].dir, dir))
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.format(subsignal.ios[0], subsignal.ios[0].dir, dir))
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if not isinstance(xdr, int) or xdr < 0:
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raise ValueError("Data rate of {!r} must be a non-negative integer, not {!r}"
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.format(subsignal.io[0], xdr))
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.format(subsignal.ios[0], xdr))
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return dir, xdr
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def resolve(subsignal, dir, xdr, name):
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if isinstance(subsignal.io[0], Subsignal):
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def resolve(resource, dir, xdr, name, attrs):
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if isinstance(resource.ios[0], Subsignal):
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fields = OrderedDict()
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for sub in subsignal.io:
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for sub in resource.ios:
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fields[sub.name] = resolve(sub, dir[sub.name], xdr[sub.name],
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name="{}__{}".format(name, sub.name))
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name="{}__{}".format(name, sub.name),
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attrs={**attrs, **sub.attrs})
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||||
return Record([
|
||||
(f_name, f.layout) for (f_name, f) in fields.items()
|
||||
], fields=fields, name=name)
|
||||
|
||||
elif isinstance(subsignal.io[0], (Pins, DiffPairs)):
|
||||
phys = subsignal.io[0]
|
||||
elif isinstance(resource.ios[0], (Pins, DiffPairs)):
|
||||
phys = resource.ios[0]
|
||||
if isinstance(phys, Pins):
|
||||
port = Record([("io", len(phys))], name=name)
|
||||
if isinstance(phys, DiffPairs):
|
||||
port = Record([("p", len(phys)),
|
||||
("n", len(phys))], name=name)
|
||||
if dir == "-":
|
||||
self._ports.append((subsignal, None, port))
|
||||
self._ports.append((resource, None, port, attrs))
|
||||
return port
|
||||
else:
|
||||
pin = Pin(len(phys), dir, xdr, name=name)
|
||||
self._ports.append((subsignal, pin, port))
|
||||
self._ports.append((resource, pin, port, attrs))
|
||||
return pin
|
||||
|
||||
else:
|
||||
|
|
@ -145,51 +150,61 @@ class ConstraintManager:
|
|||
|
||||
value = resolve(resource,
|
||||
*merge_options(resource, dir, xdr),
|
||||
name="{}_{}".format(resource.name, resource.number))
|
||||
name="{}_{}".format(resource.name, resource.number),
|
||||
attrs=resource.attrs)
|
||||
self._requested[resource.name, resource.number] = value
|
||||
return value
|
||||
|
||||
def iter_single_ended_pins(self):
|
||||
for res, pin, port in self._ports:
|
||||
for res, pin, port, attrs in self._ports:
|
||||
if pin is None:
|
||||
continue
|
||||
if isinstance(res.io[0], Pins):
|
||||
yield pin, port.io, res.extras
|
||||
if isinstance(res.ios[0], Pins):
|
||||
yield pin, port.io, attrs
|
||||
|
||||
def iter_differential_pins(self):
|
||||
for res, pin, port in self._ports:
|
||||
for res, pin, port, attrs in self._ports:
|
||||
if pin is None:
|
||||
continue
|
||||
if isinstance(res.io[0], DiffPairs):
|
||||
yield pin, port.p, port.n, res.extras
|
||||
if isinstance(res.ios[0], DiffPairs):
|
||||
yield pin, port.p, port.n, attrs
|
||||
|
||||
def should_skip_port_component(self, port, attrs, component):
|
||||
return False
|
||||
|
||||
def iter_ports(self):
|
||||
for res, pin, port in self._ports:
|
||||
if isinstance(res.io[0], Pins):
|
||||
yield port.io
|
||||
elif isinstance(res.io[0], DiffPairs):
|
||||
yield port.p
|
||||
yield port.n
|
||||
for res, pin, port, attrs in self._ports:
|
||||
if isinstance(res.ios[0], Pins):
|
||||
if not self.should_skip_port_component(port, attrs, "io"):
|
||||
yield port.io
|
||||
elif isinstance(res.ios[0], DiffPairs):
|
||||
if not self.should_skip_port_component(port, attrs, "p"):
|
||||
yield port.p
|
||||
if not self.should_skip_port_component(port, attrs, "n"):
|
||||
yield port.n
|
||||
else:
|
||||
assert False
|
||||
|
||||
def iter_port_constraints(self):
|
||||
for res, pin, port in self._ports:
|
||||
if isinstance(res.io[0], Pins):
|
||||
yield port.io.name, list(res.io[0].map_names(self._mapping, res)), res.extras
|
||||
elif isinstance(res.io[0], DiffPairs):
|
||||
yield port.p.name, list(res.io[0].p.map_names(self._mapping, res)), res.extras
|
||||
yield port.n.name, list(res.io[0].n.map_names(self._mapping, res)), res.extras
|
||||
for res, pin, port, attrs in self._ports:
|
||||
if isinstance(res.ios[0], Pins):
|
||||
if not self.should_skip_port_component(port, attrs, "io"):
|
||||
yield port.io.name, res.ios[0].map_names(self._conn_pins, res), attrs
|
||||
elif isinstance(res.ios[0], DiffPairs):
|
||||
if not self.should_skip_port_component(port, attrs, "p"):
|
||||
yield port.p.name, res.ios[0].p.map_names(self._conn_pins, res), attrs
|
||||
if not self.should_skip_port_component(port, attrs, "n"):
|
||||
yield port.n.name, res.ios[0].n.map_names(self._conn_pins, res), attrs
|
||||
else:
|
||||
assert False
|
||||
|
||||
def iter_port_constraints_bits(self):
|
||||
for port_name, pin_names, extras in self.iter_port_constraints():
|
||||
for port_name, pin_names, attrs in self.iter_port_constraints():
|
||||
if len(pin_names) == 1:
|
||||
yield port_name, pin_names[0], extras
|
||||
yield port_name, pin_names[0], attrs
|
||||
else:
|
||||
for bit, pin_name in enumerate(pin_names):
|
||||
yield "{}[{}]".format(port_name, bit), pin_name, extras
|
||||
yield "{}[{}]".format(port_name, bit), pin_name, attrs
|
||||
|
||||
def iter_clock_constraints(self):
|
||||
for name, number in self.clocks.keys() & self._requested.keys():
|
||||
|
|
@ -197,12 +212,12 @@ class ConstraintManager:
|
|||
period = self.clocks[name, number]
|
||||
pin = self._requested[name, number]
|
||||
if pin.dir == "io":
|
||||
raise ConstraintError("Cannot constrain frequency of resource {}#{} because "
|
||||
"it has been requested as a tristate buffer"
|
||||
.format(name, number))
|
||||
if isinstance(resource.io[0], Pins):
|
||||
raise ResourceError("Cannot constrain frequency of resource {}#{} because "
|
||||
"it has been requested as a tristate buffer"
|
||||
.format(name, number))
|
||||
if isinstance(resource.ios[0], Pins):
|
||||
port_name = "{}__io".format(pin.name)
|
||||
elif isinstance(resource.io[0], DiffPairs):
|
||||
elif isinstance(resource.ios[0], DiffPairs):
|
||||
port_name = "{}__p".format(pin.name)
|
||||
else:
|
||||
assert False
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue