build.dsl: replace extras= with Attrs().
This change proved more tricky than expected due to downstream dependencies, so it also includes some secondary refactoring.
This commit is contained in:
whitequark
parent
c52cd72d3e
commit
ab3f103e5a
7 changed files with 262 additions and 253 deletions
102
nmigen/vendor/lattice_ice40.py
vendored
102
nmigen/vendor/lattice_ice40.py
vendored
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@ -70,7 +70,7 @@ class LatticeICE40Platform(TemplatedPlatform):
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""",
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"{{name}}.pcf": r"""
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# {{autogenerated}}
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{% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
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{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
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set_io {{port_name}} {{pin_name}}
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{% endfor %}
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""",
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@ -110,33 +110,17 @@ class LatticeICE40Platform(TemplatedPlatform):
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"""
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]
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def iter_ports(self):
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for res, pin, port in self._ports:
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if isinstance(res.io[0], Pins):
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yield port.io
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elif isinstance(res.io[0], DiffPairs):
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if res.extras.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT":
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yield port.p
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else:
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yield port.p
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yield port.n
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else:
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assert False
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def should_skip_port_component(self, port, attrs, component):
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# On iCE40, a differential input is placed by only instantiating an SB_IO primitive for
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# the pin with z=0, which is the non-inverting pin. The pinout unfortunately differs
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# between LP/HX and UP series:
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# * for LP/HX, z=0 is DPxxB (B is non-inverting, A is inverting)
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# * for UP, z=0 is IOB_xxA (A is non-inverting, B is inverting)
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if attrs.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT" and component == "n":
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return True
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return False
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def iter_port_constraints(self):
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for res, pin, port in self._ports:
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if isinstance(res.io[0], Pins):
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yield port.io.name, list(res.io[0].map_names(self._mapping, res)), res.extras
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elif isinstance(res.io[0], DiffPairs):
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if res.extras.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT":
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yield port.p.name, list(res.io[0].p.map_names(self._mapping, res)), res.extras
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else:
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yield port.p.name, list(res.io[0].p.map_names(self._mapping, res)), res.extras
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yield port.n.name, list(res.io[0].n.map_names(self._mapping, res)), res.extras
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else:
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assert False
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def _get_io_buffer(self, m, pin, port, extras, o_invert=None):
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def _get_io_buffer(self, m, pin, port, attrs, o_invert=None):
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def _get_dff(clk, d, q):
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m.submodules += Instance("$dff",
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p_CLK_POLARITY=0,
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@ -160,9 +144,9 @@ class LatticeICE40Platform(TemplatedPlatform):
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o_O=y[bit])
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return y
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if "GLOBAL" in extras:
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is_global_input = bool(extras["GLOBAL"])
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del extras["GLOBAL"]
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if "GLOBAL" in attrs:
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is_global_input = bool(attrs["GLOBAL"])
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del attrs["GLOBAL"]
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else:
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is_global_input = False
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@ -185,7 +169,7 @@ class LatticeICE40Platform(TemplatedPlatform):
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for bit in range(len(port)):
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io_args = [
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("io", "PACKAGE_PIN", port[bit]),
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*(("p", key, value) for key, value in extras.items()),
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*(("p", key, value) for key, value in attrs.items()),
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]
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if "i" not in pin.dir:
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@ -242,56 +226,52 @@ class LatticeICE40Platform(TemplatedPlatform):
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else:
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m.submodules += Instance("SB_IO", *io_args)
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def get_input(self, pin, port, extras):
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self._check_feature("single-ended input", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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def get_input(self, pin, port, attrs):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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self._get_io_buffer(m, pin, port, attrs)
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return m
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def get_output(self, pin, port, extras):
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self._check_feature("single-ended output", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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def get_output(self, pin, port, attrs):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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self._get_io_buffer(m, pin, port, attrs)
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return m
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def get_tristate(self, pin, port, extras):
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self._check_feature("single-ended tristate", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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def get_tristate(self, pin, port, attrs):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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self._get_io_buffer(m, pin, port, attrs)
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return m
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def get_input_output(self, pin, port, extras):
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self._check_feature("single-ended input/output", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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def get_input_output(self, pin, port, attrs):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, port, extras)
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self._get_io_buffer(m, pin, port, attrs)
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return m
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def get_diff_input(self, pin, p_port, n_port, extras):
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self._check_feature("differential input", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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# On iCE40, a differential input is placed by only instantiating an SB_IO primitive for
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# the pin with z=0, which is the non-inverting pin. The pinout unfortunately differs
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# between LP/HX and UP series:
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# * for LP/HX, z=0 is DPxxB (B is non-inverting, A is inverting)
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# * for UP, z=0 is IOB_xxA (A is non-inverting, B is inverting)
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def get_diff_input(self, pin, p_port, n_port, attrs):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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self._get_io_buffer(m, pin, p_port, extras)
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# See comment in should_skip_port_component above.
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self._get_io_buffer(m, pin, p_port, attrs)
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return m
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def get_diff_output(self, pin, p_port, n_port, extras):
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self._check_feature("differential output", pin, extras,
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valid_xdrs=(0, 1, 2), valid_extras=True)
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def get_diff_output(self, pin, p_port, n_port, attrs):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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# Note that the non-inverting output pin is not driven the same way as a regular
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# output pin. The inverter introduces a delay, so for a non-inverting output pin,
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# an identical delay is introduced by instantiating a LUT. This makes the waveform
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# perfectly symmetric in the xdr=0 case.
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self._get_io_buffer(m, pin, p_port, extras, o_invert=False)
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self._get_io_buffer(m, pin, n_port, extras, o_invert=True)
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self._get_io_buffer(m, pin, p_port, attrs, o_invert=False)
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self._get_io_buffer(m, pin, n_port, attrs, o_invert=True)
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return m
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# Tristate and bidirectional buffers are not supported on iCE40 because it requires external
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