sim._pyrtl: reject very large values.
A check that rejects very large wires already exists in back.rtlil because they cause performance and correctness issues with Verilog tooling. Similar performance issues exist with the Python simulator. This commit also adjusts back.rtlil to use the OverflowError exception, same as in sim._pyrtl. Fixes #588.
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599615ee3a
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3 changed files with 31 additions and 10 deletions
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@ -70,6 +70,19 @@ class _ValueCompiler(ValueVisitor, _Compiler):
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"zmod": lambda lhs, rhs: 0 if rhs == 0 else lhs % rhs,
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}
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def on_value(self, value):
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# Very large values are unlikely to compile or simulate in reasonable time.
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if len(value) > 2 ** 16:
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if value.src_loc:
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src = "{}:{}".format(*value.src_loc)
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else:
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src = "unknown location"
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raise OverflowError("Value defined at {} is {} bits wide, which is unlikely to "
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"simulate in reasonable time"
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.format(src, len(value)))
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return super().on_value(value)
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def on_ClockSignal(self, value):
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raise NotImplementedError # :nocov:
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@ -332,14 +345,15 @@ class _StatementCompiler(StatementVisitor, _Compiler):
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self.emitter.append("pass")
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def on_Assign(self, stmt):
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gen_rhs = f"({(1 << len(stmt.rhs)) - 1} & {self.rhs(stmt.rhs)})"
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gen_rhs_value = self.rhs(stmt.rhs) # check for oversized value before generating mask
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gen_rhs = f"({(1 << len(stmt.rhs)) - 1} & {gen_rhs_value})"
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if stmt.rhs.shape().signed:
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gen_rhs = f"sign({gen_rhs}, {-1 << (len(stmt.rhs) - 1)})"
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return self.lhs(stmt.lhs)(gen_rhs)
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def on_Switch(self, stmt):
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gen_test = self.emitter.def_var("test",
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f"{(1 << len(stmt.test)) - 1} & {self.rhs(stmt.test)}")
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gen_test_value = self.rhs(stmt.test) # check for oversized value before generating mask
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gen_test = self.emitter.def_var("test", f"{(1 << len(stmt.test)) - 1} & {gen_test_value}")
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for index, (patterns, stmts) in enumerate(stmt.cases.items()):
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gen_checks = []
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if not patterns:
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