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sim._pyrtl: reject very large values.

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A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
This commit is contained in:
whitequark 2021-12-11 13:00:46 +00:00
parent 599615ee3a
commit ac13a5b3c9
3 changed files with 31 additions and 10 deletions
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11
tests/test_sim.py
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@ -840,3 +840,14 @@ class SimulatorRegressionTestCase(FHDLTestCase):
with open(os.path.devnull, "w") as f:
with sim.write_vcd(f):
sim.run()
def test_bug_588(self):
dut = Module()
a = Signal(32)
b = Signal(32)
z = Signal(32)
dut.d.comb += z.eq(a << b)
with self.assertRaisesRegex(OverflowError,
r"^Value defined at .+?/test_sim\.py:\d+ is 4294967327 bits wide, "
r"which is unlikely to simulate in reasonable time$"):
Simulator(dut)