back.verilog: remove debug code.

2018-12-13 13:42:54 +00:00 · 2018-12-13 13:42:54 +00:00 · ac498414ab
parent 90f1503c91
commit ac498414ab
1 changed files with 0 additions and 1 deletions
--- a/nmigen/back/verilog.py
+++ b/nmigen/back/verilog.py
@ -30,7 +30,6 @@ proc_clean
 write_verilog
 # Make sure there are no undriven wires in generated RTLIL.
 proc
-write_ilang x.il
 select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d
 """.format(il_text))
    if popen.returncode: