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back.verilog: remove debug code.

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whitequark 2018-12-13 13:42:54 +00:00
parent 90f1503c91
commit ac498414ab
1 changed files with 0 additions and 1 deletions
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nmigen/back/verilog.py
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@ -30,7 +30,6 @@ proc_clean
write_verilog write_verilog
# Make sure there are no undriven wires in generated RTLIL. # Make sure there are no undriven wires in generated RTLIL.
proc proc
write_ilang x.il
select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d
""".format(il_text)) """.format(il_text))
if popen.returncode: if popen.returncode: